UART

Jin-Fu Li
 Introduction

• UART (modem)
 Universal asynchronous receiver and transmitter

Host Serial Data Host

Channel
processor Modem Modem processor
1 2

• Data format
Stop Parity Data Data Data Data Data Data Data Data Start
Bit Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit

National Central University EE613 VLSI Design 2

 Block Diagram of a UART
Rcv shtreg
Serial in

Rcv datareg
Receiver
controller

Clock
Sys clock To host processor
Generator

Load XMT XMT datareg

Data reg
Byte ready Transmitter
T byte controller
1
1 Serial out
XMT shfteg

National Central University EE613 VLSI Design 3

 UART – Transmitter
Byte ready Load XMT shtreg
Load XMT Datareg Transmitter Start
Bit count data path Shift
T byte controller Clear
State Next state

Byte ready: asserted by the host processor to indicate that data bus has valid data
Load XMT Datareg: asserting transfers data bus to the transmitter data storage
register, XMT datareg
T byte: asserting initiates transmission of a byte of data, along with the stop, start,
and parity bits
Bit count: counts bits in the word during transmission
State : state of the transmitter controller state machine
Load XMT shtreg: asserting loads the contents of XMT datareg into XMT shtreg
Start: signals the start of transmission
Shift: directs XMT shtreg to shift by one bit toward the LSB and backfill with stop bit (1)
Clear : clears bit counter
Next state: the next state of the state machine controlling the data path of the transmitter
National Central University EE613 VLSI Design 4
 FSM State Diagram of Transmitter
Byte ready==0

Idle

Byte ready==1 Load XMT shtreg=1

T byte==0
waiting Start=0

Bit count ==word size +1

Clear=1 T byte==1 Start=1

sending Shift=1

National Central University EE613 VLSI Design 5

 UART – Receiver
Read not ready in Clr sample counter
Inc sample counter
Serial in Receiver Shift
Sample counter data path load
Bit counter controller error1
error2
State Next state

Read not ready in: signals that the host is not ready to receive data
Sample counter: counts the samples of a bit
Bit counter: counts the bits that have been sampled
State: state of the state machine controlling the data path of the receiver
Clr sample counter: clear sample counter
Clr bit counter: clear bit counter
Shift: causes RCV shftreg to shift towards the LSB
Load: causes RCV shftreg to transfer data to RCV datareg
Error1: asserted if host is not ready to receive data after last bit has been sampled
Error2: asserts if the stop-bit is missing
Next state: next state of the state machine controlling the data path of the receiver
National Central University EE613 VLSI Design 6
 FSM State Diagram of Receiver
Serial in==1

Idle

Serial in==1 Serial in==0 Load XMT shtreg=1

Serial in==0 Sample counter 1=3

starting Inc sample counter=1

Serial in==0 Clr sample counter=1

Clear=1 Sample counter==3

receiving Inc sample counter=1

Sample counter 1=word size -1

National Central University EE613 VLSI Design 7