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Signal and Timing Parameters I: Acknowledgements: Intel Bus Boot Camp: Howard Heck
Signal and Timing Parameters I: Acknowledgements: Intel Bus Boot Camp: Howard Heck
SI Budgets
An SI budget is a technique used to
report timing and voltage margin in
terms of voltage and timing components
(“buckets”) for all configurations and
conditions of a particular bus design.
The budget is often represented in a
spread sheet.
Margin Voltage Spec Noise Bucket Measured Voltage Measurement Error
14 100 10 56 20 (mv)
Measured
parameter
value
clock
Pre- ’00 the most common computer I/O
interface was synchronous memory transfer
Intel Xeon 100 MHz bus was just about the last
in this class
Clock distribution is a challenge – more on
this later
Edge Triggered
Clock
Flip Flop
in out
Operation input data output data
Tsetup Thold
in
Timing
Valid data must be present for a minimum amount of
time prior to the input clock edge to guarantee
successful capture of the data. This is known as
setup time, Tsetup.
Data must remain valid for a minimum amount of time
after the input clock edge to guarantee that the
proper value is captured. This is called hold time,
Thold.
Signal Parameters & Timing Class 2
9
CORE
CORE
FROM
CLK CLK
TO
D Q D Q
a b
We wish to use the clock to control the transmission of data from the latch in
the source (a) to the latch in the destination (b).
The initial clock pulse causes the source latch to release the data onto the
interconnect.
The next clock pulse causes the destination latch to capture the data that was
transmitted on the interconnect
We have 1 full clock cycle to get the data from the source to destination.
Signal Parameters & Timing Class 2
11
Tdrv_clk
(1a)
Tprop_clk
(1b)
CORE
FROM
CORE
CLK CLK
TO
D Q D Q
a b
Tprop_clk
(1b)
Tprop
(2b)
CORE
FROM
CORE
CLK CLK
TO
D Q D Q
a b
Tdrv (2a) Tsetup (2c)
Tprop
(2b)
CORE
FROM
CORE
CLK CLK
TO
D Q D Q
a b
Tdrv (2a) Tsetup (2c)
Clock Skew
Transmit
clock at
device a
Receive
clock at
device b
What happens if the clock signals at the source and destination are
not in phase?
What if the clock arrives at the destination before it reaches the source?
Vice-versa?
What are the sources of uncertainty in the phase relationship between
different clock signals?
Clock Skew: pin-to-pin variation in the timing of input clock at each
agent (source & destination, in our example) on a bus.
The net effect of clock skew is that it can
reduce the total delay that signals are allowed to have for a given
frequency target.
require larger minimum signal delays in order to avoid logic errors. (We’ll
cover this in more detail shortly.)
Signal Parameters & Timing Class 2
15
Z0 ,d
Clock Driver
Tdrv CL
a
Z0 , d
Tdrv CL
Clock Jitter
Idea
clock
Clock with
Cycle to
Cycle
Jitter
Tcycle
CLOCK
@ clk input Tdrv_clk
CLOCK(a)
@ clk output Tprop_clk
CLOCK(a) @ a
Tdrv
DATA @ a Tprop Tdrv_clk (b)
Tmargin
DATA @ b Tsetup
CLOCK(b)
@ clk output
Tprop_clk(b)
CLOCK(b) @ b
Tjitter
Tcycle Tdrv _ clk b Tprop _ clk b T jitter Tsetup Tm arg in Tprop Tdrv Tprop _ clk Tdrv _ clk 0
Define
Clock Delay
Clock Skew
Simplify
Tdrv _ clk Tprop _ clk Tdrv Tprop Tm arg in _ hold Thold Tprop _ clk b Tdrv _ clk b 0
Manufacturability Considerations
Sources of variability in silicon:
manufacturing process (e.g. silicon gate length)
operating temperature (MOS speed as temp )
operating voltage (MOS speed as voltage )
Impact: variability leads to a range of values for
driver and receiver timings
Example: Pentium® Pro GTL+ timings
Minimum driver valid delay = 0.55 ns
Maximum driver valid delay = 4.40 ns
Maximum receiver setup time = 2.20 ns
Maximum receiver hold time = 0.45 ns
Sources of interconnect variability:
Manufacturing variation (Z0, r)
Trace length variation (among 144 signals for FSB, for
example)
Setup Tm argin _ setup Tcycle,min Tdrv ,max Tsetup Tprop ,max Tskew _ setup T jitter
Hold Tm arg in _ hold Tdrv,min Tprop,min Thold Tskew _ hold
The setup equation defines the minimum clock cycle time (max
frequency) in terms of the maximum system delay terms. We want
Tmargin_setup 0.
Excessive system delays can be handled by increasing cycle time, at
the cost of reduced performance.
The hold equation defines minimum system delay requirements to
avoid logic errors due to hold violations. We want Tmargin_hold 0.
Minimum delay violations cannot be fixed by increasing cycle time.
Why?
65
10pF
Flight Time
Driver Pin into
Clock Input to System Load
Transmitting
Chip
Threshold
Tdrv Tprop
Receiver Pin
Time
Signal Parameters & Timing Class 2
25
Tco Max Tsu Clk Skew Clk Jitter Length Tflight Tcyc margin
(ns) (ns) (ns) (ns)
CPU 1 3.2 0.25 0.3 0 15.15152 11.40152
3.2 CPU 2 0.5 0.25 0.3 5 0.86 15.15152 5.041515
3.2 Chip Set 1 0.25 0.3 7 1.204 15.15152 2.197515
3.2 CPU 3 0.5 0.25 0.3 7 1.204 15.15152 2.697515
3.2 CPU 4 0.5 0.25 0.3 10 1.72 15.15152 -0.818485
-0.818485 Min margin
Tco Max Tsu Clk Skew Clk Jitter Length Tflight Tcyc margin
(ns) (ns) (ns) (ns)
3.2 CPU 1 0.5 0.25 0.3 5 0.86 15.15152 5.041515
CPU 2 3.2 0.25 0.3 0 15.15152 11.40152
3.2 Chip Set 1 0.25 0.3 2 0.344 15.15152 8.057515
3.2 CPU 3 0.5 0.25 0.3 2 0.344 15.15152 8.557515
3.2 CPU 4 0.5 0.25 0.3 7 1.204 15.15152 2.697515
2.697515 Min margin
Tco Max Tsu Clk Skew Clk Jitter Length Tflight Tcyc margin
(ns) (ns) (ns) (ns)
7 CPU 1 0.5 0.25 0.3 7 1.204 15.15152 -1.102485
7 CPU 2 0.5 0.25 0.3 0 15.15152 7.101515
Chip Set 7 0.25 0.3 2 0.344 15.15152 5.257515
7 CPU 3 0.5 0.25 0.3 4 0.688 15.15152 2.413515
7 CPU 4 0.5 0.25 0.3 7 1.204 15.15152 -1.102485
-1.102485 Min margin
CPU1 CPU4
L1=5” CPU2 CPU3
L4=3”
L3=2” Tco Min Tco Max Tsu Thld Clk Skew Clk Jitter
Chipset
(ns) (ns) (ns) (ns) (ns) (ns)
L2=2”
CPU 1 0.2 3.2 0.5 0 0.25 0.3
CPU 2 0.2 3.2 0.5 0 0.25 0.3
Chip Set -0.5 7 1 -0.1 0.25 0.3
CPU 3 0.2 3.2 0.5 0 0.25 0.3
CPU 4 0.2 3.2 0.5 0 0.25 0.3