Prepared by: Guided By:

Nagpara Bharat H. Prof. R. S. Gajare

ME EC Sem.-III.
Enrolment No.:90440704012

C. U. SHAH COLLEGE OF ENGINEERING & TECHNOLOGY,

WADHWAN CITY- 363 030
 Area of Interest & its Justification.
 Work-plan for Dissertation Phase I.
 Raw Title of the Dissertation.
 Final Title of the Dissertation.
 Scope of the Thesis.
 Supplementary Work Carried Out.
 Work to be carried out in Semester-IV
 With the advances in CMOS technology, digital signal
processing is penetrating into more and more
applications.
 CMOS technology scaling has been a primary driver of
the electronics industry.
 Minimum channel length of MOS transistors dropped
from 25 μm in 1960s to 65 nm in the year 2004.
 Advantages of CMOS
◦ has High speed
◦ requires Less area
◦ dissipates Less power
◦ low fabrication cost
 Large scope to improve existing technology or to
invent new technology.
 CMOS technologies become mainstream technologies
for mixed-signal integration due to the advantages of
high speed, low power and high integration density.
 CMOS technologies are used in various applications
◦ Cellular phones and Wireless local area networks,
◦ Optical communications,
◦ Disk drive read/write electronics,
◦ Microprocessors and memories,
◦ Circuits for Sensors,
◦ Filters and oscillators,
◦ PLLs and A/D and D/A converters
◦ etc.
 Counseling
 Literature Collection
 Literature Review
 Finalizing the Topic
 Finalizing Software
 Reporting
 Dissertation –I Final Reporting.
 In most modern communication systems
timing information, in the form of clock or
oscillator signals, plays a critical role in
system performance.
 Timing information is precious in every

communication systems.
 Timing information is provided through a

local oscillator.
 Minimizing the timing errors in system is
important.
 PLL is a circuit that reduces timing errors &

synchronizes the signal.

 Phase Locked Loops are used in most of

applications such as
◦ optical communication systems,
◦ disk drive systems,
◦ local area networks,
◦ radio transmitters and receivers,
◦ microprocessors,
◦ network routers, and
◦ digital signal processors
◦ etc.
 Why PLL?
◦ For high speed application, jitter is a problem to
communication system, as it reduces the
performance of overall circuitry.

◦ As jitter is a type of corruption that cannot be

eliminated, reducing jitter is one way to help to
improve the system performance.
 Phase-locked loops (PLLs) are widely used in
communication systems. With the continuously
expanding of market for high speed, portable
communication devices, and low power-low
noise CMOS submicron integrated circuit,
designs of PLL for different applications are in
large demand.
 The increased application of PLLs has led to the
desire to reduce the Jitter and extend the Capture
range of the PLLs.
 Phase-Locked Loop Basics.
◦ A phase-locked loop is a feedback control circuit.
 A basic form of a PLL consists of three
fundamental blocks, namely,
◦ Phase detector (PD),
◦ Loop filter,
◦ Voltage controlled oscillator (VCO),
◦ Divide by N.
 The basic block diagram is shown in
Figure1.
Figure 1: A Basic Phase Locked Loop
 Terminology of PLL
◦ Lock range:
 The range of input signal frequencies over which the loop
can maintain the lock is called as Lock Range or Tracking
Range of PLL.
◦ Capture range:
 The range of input signal frequencies over which PLL can
acquire a lock is called as Capture Range or Acquisition
Range of PLL.
◦ Pull in time:
 The total time taken by the PLL to capture the signal (or to
establish the lock) is called as Pull in Time of PLL. It is also
called as Acquisition Time of PLL.
 Non Ideal Effects in PLL
◦ Jitter in PLL:
 A jitter is the short term-term variations of a signal
with respect to its ideal position in time.
◦ Phase Noise:
 Phase noise is random variation of phase of the
signal. It is the frequency domain representation of
rapid, short term fluctuations in the phase of the
wave, caused by time domain instabilities (“jitter”).
 This dissertation is aimed at design and
implementation of a circuit for a digital phase
locked loops, characterizing the components
and discussing a method of estimating the
capture range, jitter, and phase noise.

 The dissertation will attempts to design and

implementation of PLL in sub-nanometer CMOS
technology in LT spice software which is a
graphical tool for design capture and analysis.
 Prepared a paper on ‘Phase Frequency Detector with
Charge Pump for Digital Phase Locked Loop’ and this
paper has been selected in “International Conference on
Computer Engineering and Technology (ICCET’10)” at
Jodhpur, and same paper will be published in
International Journal by organizing committee.
 Prepared a paper on ‘Design and Analysis of 100 MHz
Voltage Controlled Oscillator (VCO) for DPLL using Deep
Submicron CMOS Technology’ and this paper has been
selected in ICSSA-2011 at Vallabh-Vidyanagar, and
same paper will be published in International Journal by
organizing committee.
 Counseling with the guide regarding the design and
implementation of PLL.
 Literature Collection for design and implementation of PLL.
 Detailed study of literature material.
 Defining various Components for design and
implementation of PLL.
 After defining various Components, design and
implementation of the each Components will be created.
 Implementation of the different architectures of PLL in
LTspice and its simulation.
 Estimation of Capture Range and Jitter for the different
architectures of PLL.
 Troubleshooting and comparison of the results for
different architectures of PLL.
 Drafting of Dissertation thesis.
 Final reporting after counseling with guide.
 Submission.
Thank You