Professional Documents
Culture Documents
Сл - Лк - 10 DDCA - Ch5 Dig Func Elements - Sequental 1611 - 24 034 out
Сл - Лк - 10 DDCA - Ch5 Dig Func Elements - Sequental 1611 - 24 034 out
shamt1:0 10
Y3
2 11
10
Y2
11
01
S1:0
10
Y1
11
00
S1:0
01
10
Y0
11
Chapter 5 <4>
A3 A2 A 1 A 0 shamt1:0
DIGITAL BUILDING BLOCKS Shifter Design 2
00 S1:0
01
shamt1:0 Y3
10
0
2 11
10
Y2
11
01
S1:0
10
Y1
11
00
S1:0
01
10
Y0
11
Chapter 5 <5>
A3 A2 A 1 A 0 shamt1:0
DIGITAL BUILDING BLOCKS Shifter Design 2
00 S1:0
01
shamt1:0 Y3
10
0
2 11
10
Y2 0
11
01
S1:0
10
Y1
11
00
S1:0
01
10
Y0
11
Chapter 5 <6>
A3 A2 A 1 A 0 shamt1:0
DIGITAL BUILDING BLOCKS Shifter Design 2
00 S1:0
01
shamt1:0 Y3
10
0
2 11
10
Y2 0
11
01
S1:0
Y1
10 0
11
00
S1:0
01
10
Y0
11
Chapter 5 <7>
A3 A2 A 1 A 0 shamt1:0
DIGITAL BUILDING BLOCKS Shifter Design 2
00 S1:0
01
shamt1:0 10
Y3
2 11
10
Y2
11
00
S1:0
01
Y1
• Logical shifter: 10
11
– Ex: 11001 >> 2 = 00110
– Ex: 11001 << 2 = 00100 00
S1:0
01
10
Y0
11
Chapter 5 <8>
DIGITAL BUILDING BLOCKS Shifters as Multipliers, Dividers
• A << N = A × 2N
– Example: 00001 << 2 = 00100 (1 × 22 = 4)
– Example: 11101 << 2 = 10100 (-3 × 22 = -12)
• A >>> N = A ÷ 2N
– Example: 01000 >>> 2 = 00010 (8 ÷ 22 = 2)
– Example: 10000 >>> 2 = 11100 (-16 ÷ 22 = -4)
Chapter 5 <9>
DIGITAL BUILDING BLOCKS Multipliers
• Partial products formed by multiplying a single
digit of the multiplier with multiplicand
• Shifted partial products summed to form result
Decimal Binary
230 multiplicand 0101
x 42 multiplier x 0111
460 partial 0101
+ 920 products 0101
9660 0101
+ 0000
result 0100011
230 x 42 = 9660 5 x 7 = 35
Chapter 5 <10>
A B
DIGITAL BUILDING BLOCKS 4 x 4 Multiplier 4 4
0101
x
x 0111
8
0101
0101 P
0101
+ 0000
0100011 A3 A2 A1 A0
B0
B1
0
A3 A2 A1 A0 0
x B3 B2 B1 B0 B2
A3B0 A2B0 A1B0 A0B0
A3B1 A2B1 A1B1 A0B1 0
B3
A3B2 A2B2 A1B2 A0B2
+ A3B3 A2B3 A1B3 A0B3
0
P7 P6 P5 P4 P3 P2 P1 P0
P7 P6 P5 P4 P3 P2 P1 P0
Chapter 5 <11>
DIGITAL BUILDING BLOCKS 4 x 4 Divider
0 B3 0 B2 0 B1 A3 B0
Legend
R B
1 R B
Cout Cin Cout Cin
+
Q3 D
D
N R'
A2
0
N
1
R'
Q2 A/B = Q + R/B
A1 Algorithm:
1
R’ = 0
for i = N-1 to 0
Q1
R = {R’ << 1. Ai}
A0
D=R-B
1
if D < 0, Qi=0, R’=R
Q0
R3 R2 R1 R0
else Qi=1, R’=D
R’=R
Chapter 5 <12>
Divider
DIGITAL BUILDING BLOCKS Q N = A N / BN Start
AN = aN-1 aN-2 … a1 a0
BN = bN-1 bN-2 … b 1 b0
i = N-1,0
R=A-B
Stop
R >=0
QN = QN-1:0 Qi = 1 Qi = 0
A=R A=A
Chapter 5 <13>
DIGITAL BUILDING BLOCKS Number Systems
• Numbers we can represent using binary
representations
– Positive numbers
• Unsigned binary
– Negative numbers
• Two’s complement
• Sign/magnitude numbers
1111 1000
using 4 integer and
– Two’s complement 4 fraction bits
Chapter 5 <16>
Floating-Point Numbers
DIGITAL BUILDING BLOCKS
• Binary point floats to the right of the most significant 1
• Similar to decimal scientific notation For example:
27310 = 2.73 × 102 ± M × BE In general B=10 (base)
Floating-Point Precision
• Single-Precision: 32-bit
Sign E=2 (exponent) M=2.73 (mantissa)
1 bit 8 bits 23 bits
Floating-Point Representation 2
1 bit 8 bits 23 bits
0 00000111 110 0100 0000 0000 0000 0000
Sign Exponent Fraction
Chapter 5 <19>
DIGITAL BUILDING BLOCKS Floating-Point Representation 3
• Biased exponent: bias = 127 (011111112)
– Biased exponent = bias + exponent
– Exponent of 7 is stored as:
127 + 7 = 134 = 0x100001102
Chapter 5 <20>
DIGITAL BUILDING BLOCKS Floating-Point Example
Write -58.2510 in floating point (IEEE 754)
1. Convert decimal to binary:
58.2510 = 111010.012
Chapter 5 <21>
DIGITAL BUILDING BLOCKS Floating-Point: Special Cases
Number Sign Exponent Fraction
0 X 00000000 00000000000000000000000
∞ 0 11111111 00000000000000000000000
-∞ 1 11111111 00000000000000000000000
NaN X 11111111 non-zero
• Overflow: number too large to be represented
• Underflow: number too small to be represented
• Rounding modes:
Example: 1.100101 (1.578125) to only 3 fraction bits
– Down: 1.100
– Up: 1.101
– Toward zero: 1.100
– To nearest: 1.101 (1.625 is closer to 1.578125 than 1.5 is)
Chapter 5 <22>
DIGITAL BUILDING BLOCKS Floating-Point Addition
1. Extract exponent and fraction bits
2. Prepend leading 1 to form mantissa
3. Compare exponents
4. Shift smaller mantissa if necessary
5. Add mantissas
6. Normalize mantissa and adjust exponent if necessary
7. Round result
8. Assemble exponent and fraction back into floating-point
format
Chapter 5 <23>
DIGITAL BUILDING BLOCKS Floating-Point Addition Example
Add the following floating-point numbers:
0x3FC00000
0x40500000
1. Extract exponent and fraction bits
1 bit 8 bits 23 bits
0 01111111 100 0000 0000 0000 0000 0000
Sign Exponent Fraction
1 bit 8 bits 23 bits
0 10000000 101 0000 0000 0000 0000 0000
Sign Exponent Fraction
5. Add mantissas
0.11 × 21
+ 1.101 × 21
10.011 × 21
Chapter 5 <25>
DIGITAL BUILDING BLOCKS Floating Point Addition Example
6. Normalize mantissa and adjust exponent if necessary
10.011 × 21 = 1.0011 × 22
7. Round result
No need (fits in 23 bits)
8. Assemble exponent and fraction back into floating-point
format
S = 0, E = 2 + 127 = 129 = 100000012, F = 001100..
1 bit 8 bits 23 bits
0 10000001 001 1000 0000 0000 0000 0000
Sign Exponent Fraction
in hexadecimal: 0x40980000
Chapter 5 <26>
DIGITAL BUILDING BLOCKS Counters
• Increments on each clock edge
• Used to cycle through numbers. For example,
– 000, 001, 010, 011, 100, 101, 110, 111, 000, 001…
• Example uses:
– Digital clock displays
– Program counter: keeps track of current instruction executing
Symbol Implementation
CLK
N CLK
N N
+ Q
Q N N r
1
Reset
Reset
Chapter 5 <27>
DIGITAL BUILDING BLOCKS Shift Registers
• Shift a new bit in on each clock edge
• Shift a bit out on each clock edge
• Serial-to-parallel converter: converts serial input (Sin) to
parallel output (Q0:N-1)
Symbol: Implementation:
CLK
N
Q Sin Sout
Sin Sout
Q0 Q1 Q2 QN-1
Chapter 5 <28>
DIGITAL BUILDING BLOCKS Shift Register with Parallel Load
• When Load = 1, acts as a normal N-bit register
• When Load = 0, acts as a shift register
• Now can act as a serial-to-parallel converter (Sin to Q0:N-1) or
a parallel-to-serial converter (D0:N-1 to Sout)
D0 D1 D2 DN-1
Load
Clk
Sin 0 0 0 0 Sout
1 1 1 1
Q0 Q1 Q2 QN-1
Chapter 5 <29>
Memory Arrays
DIGITAL BUILDING BLOCKS N
Address Array
• Efficiently store large amounts of data
• 2-dimensional array of bit cells
• Each bit cell stores one bit M
• M-bit data value read/ written at each
Data
unique N-bit address:
– 2N rows and M columns
– Depth: number of rows (number of words)
– Width: number of columns (size of word)
– Array size: depth × width = 2N × M Address Data
11 0 1 0
2
Address Array 10 1 0 0
depth
01 1 1 0
• 22 × 3-bit array
3 00 0 1 1
• Number of words: 4
• Word size: 3-bits Data width
• For example, the 3-bit word stored at address 10 is 100
Chapter 5 <30>
Memory Array Bit Cells
DIGITAL BUILDING BLOCKS 10
1024-word x
Address 32-bit
bitline = 0 bitline = Z Array
wordline = 1 wordline = 0
stored stored
bit = 0 bit = 0
32
bitline = 1 bitline = Z
wordline = 1 wordline = 0 Data
stored stored
bit = 1 bit = 1
(a) (b)
2:4
Decoder bitline2 bitline1 bitline0
wordline3
11
2 stored stored stored
Address bit = 0 bit = 1 bit = 0
wordline2
10
stored stored stored
Wordline: wordline1 bit = 1 bit = 0 bit = 0
01
• like an enable stored stored stored
bit = 1 bit = 1 bit = 0
• corresponds to unique address 00
wordline0
• single row in memory array read/written Chapter 5 <31> Data2 Data1 Data0
Types of Memory
DIGITAL BUILDING BLOCKS
RAM (Random Access Memory): volatile
random (in contrast to sequential access such as a tape recorder)
• Read and written quickly
bitline
• Main memory in computer is RAM (DRAM) wordline
stored + + stored
bit = 1 bit = 0
Chapter 5 <33>
DIGITAL BUILDING BLOCKS
DDR
SDRAM
Chapter 5 <34>
DDR SDRAM
DIGITAL BUILDING BLOCKS
Максимальная
теоретическая
пропускная
Тактовспособность, МБ/с
ая
Названи частот
Тип
е чипа а
модуля шины однока
памят нальны двухкана
и, МГц й льный
режим режим
Chapter 5 <37>
DIGITAL BUILDING BLOCKS
Chapter 5 <38>
ROM Logic
DIGITAL BUILDING BLOCKS wordline
bitline
2:4
Decoder bit cell Address Data
containing 0
11 11 0 1 0
2
Address
bitline 10 1 0 0
10 depth
wordline 01 1 1 0
01 bit cell 00 0 1 1
containing 1 A1A0
00 width
A1A0 Data2 Data1 Data0 Logic with Any Memory
2:4
Decoder
wordline
Array bitline bitline2
bitline 1 0
11 3
10
wordline2
bit = 0 bit = 1 bit = 0
Data1 = A1 + A0 01
stored
bit = 1
stored
bit = 1
stored
bit = 0
wordline0
00
stored stored stored
Data0 = A1A0 bit = 0 bit = 1 bit = 1
2:4
Decoder bitline
Truth
Table 00
stored
A A1
bit = 0
A B Y 01
B A0
0 0 0 stored
0 1 0 bit = 0
1 0 0 10
1 1 1 stored
bit = 0
11
stored
bit = 1
Chapter 5 <40> Y
Example: Logic with Memory Arrays
DIGITAL BUILDING BLOCKS
Implement the following logic functions using a 22 × 3-bit
memory array:
– X = AB
– Y=A+B
– Z=AB
2:4 2:4
Decoder Decoder bitline2 bitline1 bitline0
wordline3
11 11
2 2 stored stored stored
A, B A, B bit = 1 bit = 1 bit = 0
wordline2
10 10
stored stored stored
wordline1 bit = 0 bit = 1 bit = 1
01 01
stored stored stored
bit = 0 bit = 1 bit = 0
wordline0
00 00
stored stored stored
bit = 0 bit = 0 bit = 0
X Y Z
Chapter 5 <41>
X Y Z
DIGITAL BUILDING BLOCKS Multi-ported Memories
• Port: address/data pair
• 3-ported memory
– 2 read ports (A1/RD1, A2/RD2)
– 1 write port (A3/WD3, WE3 enables writing)
• Register file: small multi-ported memory
CLK
WE3
A1 RD1
N M
A2 RD2
N M
A3 Array
N
WD3
M
Chapter 5 <42>
DIGITAL BUILDING BLOCKS SystemVerilog Memory Arrays
// 256 x 3 memory module with one read/write port
module dmem( input logic clk, we,
input logic [7:0] a,
input logic [2:0] wd,
output logic [2:0] rd);
assign rd = RAM[a];
Chapter 5 <43>
DIGITAL BUILDING BLOCKS Logic Arrays
• PLAs (Programmable logic arrays)
– AND array followed by OR array
– Combinational logic only
– Fixed internal connections
Chapter 5 <44>
PLAs
DIGITAL BUILDING BLOCKS A B C
OR ARRAY
• Y = AB ABC
Inputs
M AB
AND Implicants OR
ARRAY N ARRAY
AND ARRAY
X Y
P
Outputs
A B C
OR ARRAY
ABC
AB
AND ARRAY
Chapter 5 <45> X Y
FPGA: Field Programmable Gate Array
DIGITAL BUILDING BLOCKS
• Composed of: LEs (Logic elements): perform logic
– LUTs (lookup tables): perform
combinational logic
– Flip-flops: perform sequential
General FPGA Layout logic
– Multiplexers: connect LUTs
and flip-flops
– IOEs (Input/output elements):
interface with outside world
– Programmable interconnection:
connect LEs and IOEs
– Some FPGAs include other
building blocks such as multipliers
and RAMsChapter 5 <46>
• The Altera Cyclone IV LE has:
Altera Cyclone IV LE
DIGITAL BUILDING BLOCKS – 1 four-input LUT
– 1 registered output
– 1 combinational output
Chapter 5 <47>
LE Configuration Example
DIGITAL BUILDING BLOCKS
Show how to configure a Cyclone IV LE to perform the
following functions:
– X = ABC + ABC
– Y = AB
(A) (B) (C) (X)
data 1 data 2 data 3 data 4 LUT output
0 0 0 X 0
0 0 1 X 1
A data 1
0 1 0 X 0
B data 2
0 1 1 X 0 C
data 3 X
1 0 0 X 0
0 data 4
1 0 1 X 0 LUT
1 1 0 X 1
LE 1
1 1 1 X 0
Chapter 5 <48> LE 2
DIGITAL BUILDING BLOCKS FPGA Design Flow
Using a CAD tool (such as Altera’s Quartus II)
• Enter the design using schematic entry or an HDL
• Simulate the design
• Synthesize design and map it onto FPGA
• Download the configuration onto the FPGA
• Test the design
Chapter 5 <49>
КНУ ім.Т.Г.Шевченка ФІТ кафедра ПСТ
Computer Architecture Архітектура комп’ютерів