Gương Dòng TH Đ NG Và Tích C C

ĐẠI HỌC QUỐC GIA TP.
HỒ CHÍ MINH
ĐẠI HỌC BÁCH KHOA
NGÀNH KỸ THUẬT ĐIỆN TỬ
CHƯƠNG 5
GƯƠNG DÒNG
THỤ ĐỘNG VÀ TÍCH CỰC
Hoàng Trang
Bộ môn Kỹ Thuật Điện Tử
hoangtrang@hcmut.edu.vn
1
TP.Hồ Chí Minh 03/ 2014
Overview
Review
This chapter deals with the design of current mirrors as both
bias elements and signal processing components. Following a
review of basic current mirrors, we study cascode mirror
operation. Next, we analyze active current mirrors and describe
the properties of differential pairs using such circuits
as loads.
Following a brief review of basic concepts, we describe in this
chapter two types of current mirror:
• Passive Current Mirror.
• Active Current Mirror.
Faculty of Electronics Engineering Spring 2014 Analog Integrated Circuit Design Course
2
Outline
0. Introduction
1. Passive Current Mirror.
2. Active Curret Mirror.
3. Sumary
3
0. Introduction
Basic Ideas
• Current source: Rout =∞, the output current is independent

with the load.
• Voltage Source: Rout =0, the output voltage is independent
with the load.
• Current mirrors/sources are widely used in analog
integrated circuits.
– current source load for common source amplifiers
– tail current source for differential pairs
– bias currents for folded cascode amplifier
• The current sources can be copied from a reference master
current source, which usually comes from a band-gap
reference circuit.
4
0. Introduction
Basic Ideas
W
I D  12 μ n C ox  VGS  VTH  2
L
W R2
I Out  μ n C ox
1
2
 R1 R2 VDD  VTH  2
Simple Resistive Biasing For Current Source
5
0. Introduction
Basic Ideas
• Output current depends on
– Supply (Vdd)
– Process (W/L,VTH):VTH vary from wafer to
wafer
– Temperature (R1,R2, , )
 Output current is poorly defined
IS THERE A WAY OF GENERATING
RELIABLE CURRENTS ?
6
0. Introduction
Basic Ideas
Assume that Iref is available and pricise

How do we guarantee Iout = IREF ?
7
Outline
0. Introduction
3. Sumary
8
1. Passive Current Mirror
Basic Current Mirror
Both in saturation and neglecting the Lambda
We get
(W/L)1
I out  I REF
(W/L) 2
It allows precise copying of the current with no

dependence on process and temperature
9
Current Source & Current Sink
Current
mirror for
NMOS
Current
•IOUT1 ： current source
mirror for •IOUT2 ： current sink
PMOS
10
Multicurrent Mirrors
Replica Bias
11
Example: Current Mirror Bias
Objectives:
– Want accurate mirror ratio ITAIL/IREF
– Want large RTAIL(and small CTAIL) for good CMRR
– Want small Vmin to maximize common mode input range
12
Basic Sizing Considerations
Always use L1=L2

• Make W1/W2 or W2/W1 integer
– Use unit devices connected in parallel Matching Technique
– "m-factor" in Spice for Layout
E.g. M1 d g s b W=10u L=0.35u m=5
13
Chanel Length Modulation
While
but VDS2 may not equal VDS1
How to copy the IREF in
this case ?
14
Inaccuracy due to ΔVD
Two options
– Use device with large ro (Large L)
– Make V1 as close as possible to V2
15
Cascode Current Mirror
A cascode can help create a higher output resistance,

- e.g. to improve CMRR in a differential pair
• Even though the impedance is now high at the current mirror
output, we still need VX=VY to minimize systematic errors in
the current ratio Iout/Iref
16
Cascode Current Mirror
How do we generate Vb to ensure Vx = Vy ?
17
Solution 1
What is the minimum allowable

voltage across the current source?
18
Solution 1
V P,min = VN – VTH
= VGS0 + VGS1 – VTH
= (Vgs0 – VTH ) + (Vgs1 – VTH ) + VTH
Iout keep track IREF at higher accuracy but the

minimum level Vp is higher by VTH
19
Headroom Issue
20
Solution 2
Low Voltage Cascode Current Mirror
M1 and M2 are in saturation:

M2: Vb – VTH2 ≤ VX (= VGS1)
M1: = VGS1 – VTH1 ≤ VA (= Vb - VGS1)
 VGS2 + (VGS1 – VTH1 ) ≤ Vb ≤ VGS2 – VTH2
Use some kind of "magic battery" that sets the cascode gate
potential such that VOUTmin= 2VOV (minimum possible)
• "High swing" bias
21
Method 1
M1 and M2 are in saturation:

Vb,min = VGS2 + (VGS1 – VTH1 )
Select: VGS5 ≈ VGS2
VDS6 = VGS5 - Rb I1 ≈VGS1 - VTH1
• Sensitive to body effect

• The magnitude of RbI1
is not well-controlled
22
Method 2
M7 : large (W/L)7 so that VGS7≈VTH7

VDS6 ≈ VGS6 – VTH7
Vb = VGS5 + VGS6 – VTH7
• Use diode-connected
transistor M7 instead of Rb
• Sensitive to body effect
23
Method 3
If MS is biased at a very low current

density,ID/(W/L),
then VGSS ≈ VTHS ≈ VTH3, i.e., VN’≈ VN − VTH3, and
VB = VGS1 + VGS0 − VTH3 − VGS3 = VGS1 − VTH3
implying that M2 is at the edge of the triode region.
In this topology, however,
VDS2≠ VDS1
If the body effect is considered for M0 , MS and M3,
it is different to guarantee that M2 operates in
saturation.
24
Method 4
25
Method 4
Insensitive to body effect

26
Outline
0. Introduction
3. Sumary
27
2. Active Current Mirror
Multistage Amplifier
Current mirrors could be used in circuitry that provides the DC bias
current to the active circuits. They can also be actively involved in
processing the signal.
28
Single-ended Output Differential Amplifier
29
I out
Gm   R out  (1  g m2 ro2 )(1 / g m1 )  ro2
Vin
 2 ro2  (1 / g m1 )  2 ro2
Calculate Gm g .V /2 g
 m1 in  m1 Calculate Rout
Vin 2 Thus , R out  2 ro2 // ro4
Assuming γ = 0
| A v |  G m .R out | A v |  G m2 . 2ro2 // ro4
30
Calculate Vp /Vin Calculate Vout /Vp
1 ro4 1 ro4 Vout 1 G m2 .ro2
R eq    (1  )
Vp  r
G m2 G m2 .ro2 G m2 ro2
1 o4
r
ro2
1 o4
VP R eq r
  o2 G m2 .ro2
Vin R  1 r
2  o4
 r
eq G
m1 ro2 1 o4
ro2
Note: if ro4 → 0, Vp /Vin → 1/2, and if

ro4 →∞, Vp /Vin → 1.
Calculate Vout/Vin
ro4
1
Vout Vout Vp G m2 .ro2 ro2
G m2 .ro2 .ro4 G m2
 .  ro4 . ro2   [(2ro2 )//ro4 ]
Vin Vp Vin 2ro2  ro4 2
2 1
ro2 ro4
31
The small signal drain

current of M1 is “wasted”.
32
Differential Amplifier with Active Current Mirror Load
Operation:
+ If Vin1 << Vin2, M1 is off and so are M3 and M4. M2 and
M5 operate in triode region, carrying zero current. Thus, Vout
= 0.
+ As Vin1 approaches Vin2 for a small difference, M2 and M4
are saturated, providing a high gain.
+ As Vin1 becomes more positive than Vin2, ID1, |ID3|, and |
ID4| increase and ID2 decreases, eventually driving M4 into
the triode region.
+ If Vin1 >> Vin2, M2 turns off, M4 operates in deep triode
region with zero current, and Vout = VDD.
 The choice of the input common-mode voltage:

For M2 to be saturated, Vout ≥ Vin,CM − VTH. Thus, to allow
maximum output swings, the input CM level must be as low as
possible, with Vin,CM = VGS1,2 + VDS5,min
33
Differential Amplifier with Active Current Mirror Load
Summary
Large signal Analysis
34
Common mode input range
35
Small Signal Circuit Transconductance
36
Small Signal Output Resistance
VX VX
IX  2 1 
2ro1,2  //r01,2 ro4
G m3
37
Small Signal Gain
For 2ro1,2 >> (1/gm3)||ro3, we have Rout ≈ ro2 || ro4
The Avand Routare the

Same as simple constant
current load commonsource stage.
| Av | = GmRout = gm1,2 (ro2 || ro4)
38
Alternative Method
Thevenin equivalent
39
Alternative Method
Thevenin equivalent
Veq  g m1,2 .ro1,2 .Vin

Calculate Veq and Req
R eq  2ro1,2
40
Alternative Method
Thevenin equivalent
41
Common Mode
The CM gain is defined in terms of

the single-ended output component
produced by the input CM change:
Vout
A CM  Vin
42
Common Mode
1 ro3,4
//
2g m3,4 2
A CM   . Even with perfect symmetry,
1
2  RSS the output signal is corrupted
2g m1,2
by input CM variations, a
g m1,2 drawback that does not exist
1
  . in the fully differential circuits
1 2 g m1,2 . RSS g m3,4
43
Common Mode
1 ro3,4
//
2g m3,4 2
A CM   . Even with perfect symmetry,
1
2  RSS the output signal is corrupted
2g m1,2 by input CM variations, a
g m1,2 drawback that does not exist
1
  . in the fully differential circuits
1 2 g m1,2 . RSS g m3,4
CMRR
A DM g m3,4 (1 2g m1,2R SS )
CMRR   g m1,2 (ro1,2//ro3,4 ).  g m3,4 (1 2g m1,2R SS )(ro1,2//ro3,4 )
A CM g m1,2
44
References
[1] Phillip E.Allen, Douglas R.Holberg, “CMOS Analog Circuit Design”,

2nd Edition, Oxford Univeristy Press, 2002.
[2] Behad Razavi. "Design of Analog CMOS Integrated Circuits",

International Edition, Electrical and Computer Engineering Series,
McGraw-Hill, 2001
[3] R. Jacob Baker. "CMOS Circuit Design, Layout, and Simulation", 3rd
Edition, IEEE Press Series on Microelectronic Systems, A Join Wiley &
Son, 2010 .

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ĐẠI HỌC QUỐC GIA TP.

1. Passive Current Mirror.

2. Active Curret Mirror.

• Current source: Rout =∞, the output current is independent

Simple Resistive Biasing For Current Source

Assume that Iref is available and pricise

1. Passive Current Mirror.

2. Active Curret Mirror.

It allows precise copying of the current with no

Always use L1=L2

A cascode can help create a higher output resistance,

How do we generate Vb to ensure Vx = Vy ?

What is the minimum allowable

Iout keep track IREF at higher accuracy but the

M1 and M2 are in saturation:

• "High swing" bias

M1 and M2 are in saturation:

• Sensitive to body effect

M7 : large (W/L)7 so that VGS7≈VTH7

If MS is biased at a very low current

Insensitive to body effect

1. Passive Current Mirror.

2. Active Curret Mirror.

Note: if ro4 → 0, Vp /Vin → 1/2, and if

The small signal drain

 The choice of the input common-mode voltage:

Large signal Analysis

For 2ro1,2 >> (1/gm3)||ro3, we have Rout ≈ ro2 || ro4

The Avand Routare the

| Av | = GmRout = gm1,2 (ro2 || ro4)

Veq  g m1,2 .ro1,2 .Vin

The CM gain is defined in terms of

[1] Phillip E.Allen, Douglas R.Holberg, “CMOS Analog Circuit Design”,

[2] Behad Razavi. "Design of Analog CMOS Integrated Circuits",

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