Integrating OVM Components

into Testbenchs
Best Practices for Vertical
Integrations
 Integration Pitfalls
• Duplication of interface related logic could result
in doubling (or worse) our samples per clock
edge.
• Multiple OVM Toplevels within a given
architecture can lead to multiple ovm_top
instances potentially confusing the set_config
process
• Having OVM instantiated in the same hierarchy
as the DUT means that any change in OVM
code results in unnecessarily recompiling the
DUT code as well
 OVM Test (OVM Toplevel) DUT Toplevel
Interface
Block W Architecture
Block W OVM Testbench
Registry
Module W OVC A DUT W C

Interface A OVC B

Interface B OVC

Interface C OVC

class w_block_test1 extends ovm_test; class w_block_tb1 extends ovm_env; NEED DEMO CODE HERE FOR DUT Top Level!!!
interface_a_ovc a_ovc;
w_block_tb1 w_tb; interface_b_ovc b_ovc;
interface_c_ovc c_ovc;
...
module_w_ovc w_ovc;
virtual function connect();
w_tb.a_ovc.assign_vi(<registry call>); ...
w_tb.b_ovc.assign_vi(<registry call>);
w_tb.c_ovc.assign_vi(<registry call>); virtual function connect();
endfunction : connect
a_ovc.analysis_port.connect(w_ovc.a_imp);

endclass : w_block_tb1
b_ovc.analysis_port.connect(w_ovc.b_imp);

c_ovc.analysis_port.connect(w_ovc.c_imp);
endfunction : connect

endclass : w_block_tb1
 OVM Test (OVM Toplevel) DUT Toplevel
Interface
Block X Architecture
Block X OVM Testbench
Registry
Module X OVC

B
Interface B OVC
D DUT X C
Interface D OVC

Interface C OVC

class x_block_test1 extends ovm_test; class x_block_tb1 extends ovm_env; NEED DEMO CODE HERE FOR DUT Top Level!!!
interface_a_ovc a_ovc;
x_block_tb1 x_tb; interface_b_ovc b_ovc;
interface_c_ovc c_ovc;
...
module_w_ovc w_ovc;
virtual function connect();
x_tb.a_ovc.assign_vi(<registry call>); ...
x_tb.b_ovc.assign_vi(<registry call>);
x_tb.c_ovc.assign_vi(<registry call>); virtual function connect();
endfunction : connect
a_ovc.analysis_port.connect(w_ovc.a_imp);

endclass : x_block_tb1
b_ovc.analysis_port.connect(w_ovc.b_imp);

c_ovc.analysis_port.connect(w_ovc.c_imp);
endfunction : connect

endclass : x_block_tb1
 OVM Test (OVM Toplevel) DUT Toplevel
Interface
Block W OVM Testbench
Registry
Module W OVC A DUT W C

E
Interface A OVC
Sub-System Architecture

H G
Interface B OVC

T N
Interface C OVC

O
Block X OVM Testbench

R Y
Module X OVC
B

W A
Interface B OVC D DUT X C

Interface D OVC

Interface C OVC

W
 Unnecessary Duplication
• By copying the block level testbench
OVC’s into the Sub-System environment,
we’ve duplicated the shared interface
OVC’s
– Every sample is now doubled
– BOTH interface OVC’s need to be connected
to the interface registry
 OVM Test (OVM Toplevel) DUT Toplevel
Interface
Sub-System OVM Testbench Registry
A DUT W C
Interface A OVC B
Sub-System Architecture

Sub-System OVC
Module W OVC

Interface B OVC

Interface C OVC

Module X OVC

Interface D OVC D DUT X C

THE RIGHT WAY

 Sub-System OVC
class subsystem_ovc extends ovm_env;
interface_b_ovc b_ovc;
interface_c_ovc c_ovc; class subsystem_tb extends ovm_env;
interface_a_ovc a_ovc;
module_w_ovc w_ovc; interface_f_ovc f_ovc;
module_x_ovc x_ovc;

subsystem_ovc sub_ovc;
ovm_analysis_export #(A_SEQ_ITEM) a_export;
ovm_analysis_export #(D_SEQ_ITEM) d_export; ...

... virtual function connect();

a_ovc.analysis_port(sub_ovc.a_export);
virtual function connect(); f_ovc.analysis_port(sub_ovc.f_export);
b_ovc.analysis_port.connect(w_ovc.b_imp); endfunction : connect
b_ovc.analysis_port.connect(x_ovc.b_imp);
c_ovc.analysis_port.connect(w_ovc.c_imp); endclass : subsystem_tb
c_ovc.analysis_port.connect(x_ovc.c_imp);
a_export.connect(w_ovc.a_imp);
d_export.connect(x_ovc.d_imp);
endfunction : connect

endclass : subsystem_ovc

You can avoid burrowing into an ovc

by using TLM exports
 OLD SLIDES
AFTER THIS ONE
 class w_block_tb1 extends ???;
interface_a_ovc a_ovc;
Block W OVM Testbench interface_b_ovc b_ovc;
interface_c_ovc c_ovc;
Module W OVC
A DUT W C module_w_ovc w_ovc;

Interface A OVC B ...

Interface B OVC virtual function connect();

a_ovc.analysis_port.connect(w_ovc.a_imp);
b_ovc.analysis_port.connect(w_ovc.b_imp);
Interface C OVC c_ovc.analysis_port.connect(w_ovc.c_imp);
endfunction : connect

endclass : w_block_tb1

Block X OVM Testbench class x_block_tb1 extends ???;

interface_b_ovc b_ovc;

Module X OVC B DUT X D

interface_d_ovc b_ovc;

module_x_ovc x_ovc;
C
Interface B OVC
...

Interface C OVC virtual function connect();

b_ovc.analysis_port.connect(w_ovc.b_imp);
d_ovc.analysis_port.connect(w_ovc.d_imp);
Interface D OVC
endfunction : connect

endclass : x_block_tb1
 Sub-System Level OVC Instantiation

Sub-System OVM Testbench Sub-System DUT

Interface A OVC

Sub-System OVC
A DUT W C
Module W OVC
B

Interface C OVC

Interface B OVC

B DUT X D
Module X OVC

Interface D OVC