Date Nov 2020

Course : Microprocessor
B Tech ECE
Poonam Agarwal,
Assistant Professor
School of Computer & Systems Sciences
JNU, New Delhi -110067
India
 TRAP
• TRAP is the only non-maskable interrupt.
– It does not need to be enabled because it cannot be
disabled.
• It has the highest priority amongst interrupts.
• It is edge and level sensitive.
– It needs to be high and stay high to be recognized.
– Once it is recognized, it won’t be recognized again until it goes
low, then high again.

• TRAP is usually used for power failure and

emergency shutoff.
 Internal Interrupt Priority
• Internally, the 8085 implements an interrupt
priority scheme.
– The interrupts are ordered as follows:
• TRAP
• RST 7.5
• RST 6.5
• RST 5.5
• INTR

– However, TRAP has lower priority than the HLD signal

used for DMA.
 The 8085 Interrupts
Interrupt Masking Triggerin
Maskable Vectored Memory
Name g
Method Method
Level
INTR Yes DI / EI No No
Sensitive
RST 5.5 / DI / EI Level
Yes Yes No
RST 6.5 SIM(set Sensitive
interrupt
mask)
DI / EI Edge
RST 7.5 Yes Yes Yes
SIM Sensitive
Level &
TRAP No None Yes No Edge
Sensitive
Set interrupt mask

Read interrupt mask : For

Pending interrupt
 Additional Concepts and Processes
• Programmable Interrupt Controller 8259 A

– A programmable interrupt managing device

• It manages 8 interrupt requests.
• It can vector an interrupt anywhere in memory without
additional H/W.
• It can support 8 levels of interrupt priorities.
• The priority scheme can be extended to 64 levels using a
hierarchy of 8259 device.
 The Need for the 8259A
• The 8085 INTR interrupt scheme presented earlier has a
few limitations:
– The RST instructions are all vectored to memory page 00H,
which is usually used for ROM.
– It requires additional hardware to produce the RST
instruction opcodes.
– Priorities are set by hardware.

• Therefore, we need a device like the 8259A to expand

the priority scheme and allow mapping to pages other
than 00H. Interrupt Vector
RST 5.5 002CH
RST 6.5 0034H
RST 7.5 003CH
 Operating of the 8259A
•The 8259A requires the microprocessor to provide 2 control words
to set up its operation. After that, the following sequence occurs:

1. One or more interrupts come in.

2. The 8259A resolves the interrupt priorities based on its internal
settings
3. The 8259A sends an INTR signal to them
microprocessor.
4. The microprocessor responds with an INTA signal and turns off
the interrupt enable flip flop.
5. The 8259A responds by placing the op-code for the CALL
instruction (CDH) on the data bus.
 Operating of the 8259A

6. When the microprocessor receives the op-code for CALL

instead of RST, it recognizes that the device will be sending
16 more bits for the address.
7. The microprocessor sends a second INTA signal.
8. The 8259A sends the high order byte of the ISR’s address.
9. The microprocessor sends a third INTA signal.
10. The 8259A sends the low order byte of the ISR’s address.
11. The microprocessor executes the CALL instruction and jumps
to the ISR.
 Direct Memory Access
• This is a process where data is transferred between two peripherals
directly without the involvement of the microprocessor.

– This process employs the HOLD pin on the

microprocessor

• The external DMA controller sends a signal on the HOLD

pin to the microprocessor.

• The microprocessor completes the current operation and

sends a signal on HLDA and stops using the buses.

• Once the DMA controller is done, it turns off the HOLD

signal and the microprocessor takes back control of the
buses.
DMA data transfer
Serial I/O and Data
Communication
 Basic Concepts in Serial I/O
• Interfacing requirements:
– Identify the device through a port number.
• Memory-mapped.
• Peripheral-mapped.
– Enable the device using the Read and Write control
signals.
• Read for an input device.
• Write for an output device.
– Only one data line is used to transfer the information
instead of the entire data bus.
• Block diagram : Serial I/O interfacing
 Basic Concepts in Serial I/O
• Controlling the transfer of data:
– Microprocessor control.
• Unconditional, polling, status check, etc.
– Device control.
• Interrupt.
 Synchronous Data Transmission
• The transmitter and receiver are synchronized.
– A sequence of synchronization signals is sent before the
communication begins.

• Usually used for high speed transmission.

• More than 20 K bits/sec.

• Message based.
– Synchronization occurs at the beginning of a long
message.
Asynchronous Data Transmission
• Transmission occurs at any time.

• Character based.
– Each character is sent separately.

• Generally used for low speed transmission.

– Less the 20 K bits/sec.
Asynchronous Data Transmission
• Follows agreed upon standards:
– The line is normally at logic one (mark).
• Logic 0 is known as space.
– The transmission begins with a start bit (low).
– Then the seven or eight bits representing the
character are transmitted.
– The transmission is concluded with one or two
stop bits. Start
D0 D1 D2 D3 D4 D5 D6 D7 Stop

One Character

Time
Synchronous and Asynchronous
 Simplex and Duplex
• Simplex.
Transmission
– One-way transmission.
– Only one wire is needed to connect the two devices
– Like communication from computer to a printer.

• Half-Duplex.
– Two-way transmission but one way at a time.
– One wire is sufficient.
– E.g. Walkie Talkie

• Full-Duplex.
– Data flows both ways at the same time.
– Two wires are needed.
 Rate of Transmission
• For parallel transmission, all of the bits are sent at
once.
• For serial transmission, the bits are sent one at a
time.
– Therefore, there needs to be agreement on how “long”
each bit stays on the line.

• The rate of transmission is usually measured in

bits/second or baud.
 Length of Each Bit
• Given a certain baud rate, how long should
each bit last?
– Baud = bits / second.
– Seconds / bits = 1 /baud.
– At 1200 baud, a bit lasts 1/1200 = 0.83 m Sec.

Q: At 1000 baud, a bit lasts 1/1000 = 1 m Sec.

 Transmitting a Character
• To send the character A over a serial
communication line at a baud rate of 56.6 K:
– ASCII for A is 41H = 01000001.
– Must add a start bit and two stop bits:
• 11 01000001 0
– Each bit should last 1/56.6K = 17.66  Sec.
• Known as bit time.
– Set up a delay loop for 17.66  Sec and set the
transmission line to the different bits for the duration of the
loop.
 Error Checking
• Various types of errors may occur during
transmission.
– To allow checking for these errors, additional
information is transmitted with the data.

• Error checking techniques:

– Parity Checking.
– Checksum.

• These techniques are for error checking not

correction.
– They only indicate that an error has occurred.
– They do not indicate where or what the correct
information is.
 Parity Checking
• Make the number of 1’s in the data Odd or Even.
– Given that ASCII is a 7-bit code, bit D7 is used to carry
the parity information.

– Even Parity
• The transmitter counts the number of ones in the data. If there
is an odd number of 1’s, bit D7 is set to 1 to make the total
number of 1’s even.
• The receiver calculates the parity of the received message, it
should match bit D7.
– If it doesn’t match, there was an error in the transmission.
 Checksum
• Used when larger blocks of data are being
transmitted.

• The transmitter adds all of the bytes in the

message without carries. It then calculates the 2’s
complement of the result and send that as the
last byte.

• The receiver adds all of the bytes in the message

including the last byte. The result should be 0.
– If it isn’t an error has occurred.
 10-5 CHECKSUM

The last error detection method we discuss here is

called the checksum. The checksum is used in the
Internet by several protocols although not at the data
link layer. However, we briefly discuss it here to
complete our discussion on error checking

Topics discussed in this section:

Idea
One’s Complement
Internet Checksum

10.
 Example 10.18

Suppose our data is a list of five 4-bit numbers that we

want to send to a destination. In addition to sending these
numbers, we send the sum of the numbers. For example, if
the set of numbers is (7, 11, 12, 0, 6), we send (7, 11, 12, 0,
6, 36), where 36 is the sum of the original numbers. The
receiver adds the five numbers and compares the result
with the sum. If the two are the same, the receiver assumes
no error, accepts the five numbers, and discards the sum.
Otherwise, there is an error somewhere and the data are
not accepted.

10.
 Example 10.19

We can make the job of the receiver easier if we send the

negative (complement) of the sum, called the checksum. In
this case, we send (7, 11, 12, 0, 6, −36). The receiver can
add all the numbers received (including the checksum). If
the result is 0, it assumes no error; otherwise, there is an
error.

10.
Standards in Serial I/O

IEEE Standards
• IEEE: Institute of Electrical and Electronics Engineers

• De Facto standards

In Serial I/O:

Either Current : 20mA or 60mA Current loop

Or Voltage : RS-232C
 RS 232
• A communication standard for connecting
computers to the printers, modems, etc.
– The most common communication standard.
– Defined in the 1950’s.
– It uses voltages between +15 and –15 V.
– Restricted to speeds less than 20 K baud.
– Restricted to distances of less than 50 feet (15 m).

• The original standard used 25 wires to connect the two

devices.
– However, in reality only three of these wires are needed.
DTE-DCE using RS-232

Terminal Modem
RS -232C connections

RS -232 Connections :a)DTE to DCE b) DTE to DTE

 Software-Controlled Serial Transmission
• The main steps involved in serially transmitting a
character are:
– Transmission line is at logic 1 by default.
– Transmit a start bit for one complete bit length.
– Transmit the character as a stream of bits with
appropriate delay.
– Calculate parity and transmit it if needed.
– Transmit the appropriate number of stop bits.
– Transmission line returns to logic 1.
 0100
1001

Start 1-bits
Stop 2-bits

8-bits

1200 Baud :delay between two consecutive bits

is 0.833ms
 Software-Controlled Serial Reception
• The main steps involved in serial reception are:
– Wait for a low to appear on the transmission line.
• Start bit
– Read the value of the line over the next 8 bit lengths.
• The 8 bits of the character.
– Calculate parity and compare it to bit 8 of the character.
• Only if parity checking is being used.
– Verify the reception of the appropriate number of stop
bits.
 The 8085 Serial I/O Lines
• The 8085 Microprocessor has two serial I/O
pins:
– SOD – Serial Output Data
– SID – Serial Input Data

• Serial input and output is controlled using

the RIM and SIM instructions respectively.
 SIM and Serial Output
• As was discussed in Chapter 12, the SIM
instruction has dual use.
– It is used for controlling the maskable interrupt
process
– For the serial output process.
• The figure below shows how SIM uses the
accumulator for Serial Output.
7 6 5 4 3 2 1 0

M7.5

M6.5

M5.5
MSE
SDO

R7.5
SDE
XXX
Serial Output Data 0 – Disable SOD
1 – Enable
SOD
 RIM and Serial Input
• Again, the RIM instruction has dual use
– Reading the current settings of the Interrupt
Masks
– Serial Data Input

• The figure shows how the RIM instruction

uses the Accumulator for Serial Input
7 6 5 4 3 2 1 0

M5.5
M7.5
M6.5
P6.5
P7.5

P5.5
SDI

IE
Serial Input Data
 Ports?

• Using the SOD and SID pins, the user would

not need to bother with setting up input and
output ports.
– The two pins themselves can be considered as the
ports.
– The instructions SIM and RIM are similar to the
OUT and IN instructions except that they only deal
with the 1-bit SOD and SID ports.
 Example
• Transmit an ASCII character stored in
register B using the SOD line.
SODDATA MVI C, 0BH ; Set up counter for 11 bits
XRA A ; Clear the Carry flag
NXTBIT MVI A, 80H ; Set D7 =1
RAR ; Bring Carry into D7 and set D6 to
1
SIM ; Output D7 (Start bit)
XRA Exclusive
or with CALL BITTIME
Accumulator STC ; Set Carry to
1 MOV A, B ; Place character in A
1(exor)1=1.1’+ RAR ; Shift D0 of the character to the carry
1’.1=0 Shift 1 into bit D7
MOV B, A ; Save the interim result
DCR C ; decrement bit counter
1(Exor)0=1.0’+ JNZ NXTBIT
1’.0=1C RET
• 1
• 1000 0000 0

• 0
• 1100 0000

• 0
• 0000 0011 000 0000
• 1
• 0000 0001 1000 0000
• Software Serial I/O needs:

1. Input port and output port for interfacing

2. Data transmission: MPU converts parallel word
to serial bits
3. Reception, MPU converts serial to parallel
 8251 USART

Universal Synchronous/Asynchronous
Receiver/Transmitter
 8251A

• The 8251A is a programmable serial communication

interface chip designed for synchronous and asynchronous
serial data communication.

• It supports the serial transmission of data.

• It is packed in a 28 pin DIP.

 Input signals to Control signals
• CS : Chip Select : when this signal goes low, the 8251 A is selected by the MPU for communication. This is usually
connected to a decoded address bus.

• C/D Control/Data: When this signal is high, the control register or the status register is addressed : when it is low, the
data buffer is addressed. The control register and status register are differentiated by WR and RD Signals respectively

• WR: write : when this signal goes low: the MPU either writes in the control register or sends output to the data buffer.

• RD : Read : when this signal goes low, the MPU either reads a status from the status register or accepts the input data
from the data buffer.

• Reset : A high on this input resets the 8251A

• and forces it into the idle mode.

• CLK: Clock: This is the clock input

• usually connected to the system clock.
•
Architecture
• Control Register : This 16-bit register for a control word consists of two
independent bytes : the first byte is called the mode instruction and second byte
: command instruction . The register can be accessed with C/D-bar is high

• Status register : This input register checks the ready status of a peripheral. This
register is addressed as an input port when C/D-bar pin is high.

• Data Buffer : this bidirectional register can be addressed as an input port and an
output port when the C/D bar pin is low.
Control signal
Pin details
Architeture - details
• The functional block diagram of 8251A consists five
sections. They are:

• Read/Write control logic

• Transmitter
• Receiver
• Data bus buffer
• Modem control.
 Read/Write control logic

• The Read/Write Control logic interfaces the 8251A with CPU,

determines the functions of the 8251A according to the
control word written into its control register.

• It monitors the data flow.

• This section has three registers and they are control register,
status register and data buffer.

• The active low signals RD, WR, CS and C/D(Low) are used for
read/write operations with these three registers.
 Read/Write control logic cntd…

• When C/D(low) is high, the control register is selected

for writing control word or reading status word.

• When C/D(low) is low, the data buffer is selected for

read/write operation.

• When the reset is high, it forces 8251A into the idle

mode.

• The clock input is necessary for 8251A for

communication with CPU and this clock does not
control either the serial transmission or the reception
rate.
 Transmitter
• The transmitter section accepts parallel data from CPU
and converts them into serial data.

• The transmitter section is double buffered, i.e., it has a

buffer register to hold an 8-bit parallel data and another
register called output register to convert the parallel data
into serial bits.

• When output register is empty, the data is transferred

from buffer to output register. Now the processor can
again load another data in buffer register.
 Transmitter cntd…
• TxRDY TXEMPTY TxC
• If buffer register is empty, then TxRDY goes to high.

• If output register is empty then TxEMPTY goes to high.

• The clock signal, TxC (low) controls the rate at which the bits
are transmitted by the USART.
 Receiver
• The receiver section accepts serial data and convert them
into parallel data

• The receiver section is double buffered, i.e., it has an input

register to receive serial data and convert to parallel, and a
buffer register to hold the parallel data.

• When the RxD line goes low, the control logic assumes it as
a START bit, waits for half a bit time and samples the line
again.

• If the line is still low, then the input register accepts the
following bits, forms a character and loads it into the buffer
register.
 Receiver cntd…
• RxRDY RxC SYNDET/BRKDET
• The CPU reads the parallel data from the buffer register.
• When the input register loads a parallel data to buffer
register, the RxRDY line goes high.
• The clock signal RxC (low) controls the rate at which
bits are received by the USART.
• During asynchronous mode, the signal SYNDET/BRKDET
will indicate the break in the data transmission.
• During synchronous mode, the signal SYNDET/BRKDET
will indicate the reception of synchronous character.
 8251 mode register

7 6 5 4 3 2 1 0 Mode register

Number of Baud Rate

Stop bits Parity enable
0: disable 00: Syn. Mode
00: invalid 1: enable 01: x1 clock
01: 1 bit 10: x16 clock
10: 1.5 bits Character length 11: x64 clock
11: 2 bits
00: 5 bits
01: 6 bits
Parity 10: 7 bits
0: odd 11: 8 bits
1: even
8251 command register

EH IR RTS ER SBRK RxE DTR TxE

TxE: transmit enable

DTR: data terminal ready
RxE: receiver enable
SBPRK: send break character
ER: error reset
RTS: request to send
IR: internal reset
EH: enter hunt mode
 8251 status register

DSR SYNDET FE OE PE TxEMPTYRxRDY TxRDY

TxRDY: transmit ready

RxRDY: receiver ready
TxEMPTY: transmitter empty
PE: parity error
OE: overrun error
FE: framing error
SYNDET: sync. character detected
DSR: data set ready
8251 interfaced with 8085
KEYBOARD/DISPLAY
CONTROLLER - 8279
 Keyboard and display interface
• 8279 is a hardware approach to interface a matric
keyboard and a multiplexed display of seven
segments LEDs.

• The disadvantage of software approach is that the

microprocessor is occupied a considerable amount of
time in checking the keyboard and refreshing the
display. The 8279 relieves the processor from these
two tasks.

• The trade of : production cost vs. the processor time

and the software development cost.
Features of 8279

The important features of 8279 are:

• keyboard and display operations.

• Scanned mode.

• 8-character keyboard FIFO.

• 16-character display.

•
Sections
• Keyboard
• Display
• Scan
• CPU interface
 Keyboard section
• The keyboard section consists of eight return lines RL0 - RL7 that can be
connected to the columns of a keyboard matrix.
• It has two additional input : shift and control/strobe. The keys are
automatically debounced.
• The two operating modes of keyboard section are 2-key lockout and N-key
rollover.
• In the 2-key lockout mode, if two keys are pressed simultaneously, only the
first key is recognized.
• In the N-key rollover mode simultaneous keys are recognized and their
codes are stored in FIFO.
• The keyboard section also have an 8 x 8 FIFO
• (First In First Out) RAM.
• The FIFO can store eight key codes in the
• scan keyboard mode. The status of the shift key
• and control key are also stored along with key code.
• The 8279 generate an interrupt request
Display section
• The display section has eight output lines divided into two groups
A0-A3 and B0-B3.
• The output lines can be used either as a single group of eight lines
or as two groups of four lines, in conjunction with the scan lines for
a multiplexed display.
• The output lines are connected to the anodes through driver
transistor in case of common cathode 7-segment LEDs.
• The cathodes are connected to scan lines through driver transistors.
• The display can be blanked by BD (low) line.
• The display section consists of 16 x 8
• display RAM. The CPU can read from
• or write into any location of the display
• RAM.
 Scan section
• The scan section has a scan counter and four scan lines, SL0 to
SL3.
• In decoded scan mode, the output of scan lines will be similar
to a 2-to-4 decoder.
• In encoded scan mode, the output of scan lines will be binary
count, and so an external decoder should be used to convert
the binary count to decoded output.
• The scan lines are common for keyboard and display.
• The scan lines are used to form the rows of a
• matrix keyboard and also connected
• to digit drivers of a multiplexed display,
• to turn ON/OFF.
CPU/MPU interface section
• The CPU interface section takes care of data transfer between 8279
and the processor.
• This section has eight bidirectional data lines DB0 to DB7 for data
transfer between 8279 and CPU.
• It requires two internal address A =0 for selecting data buffer and A
= 1 for selecting control register of 8279.
• The control signals WR (low), RD (low), CS (low) and A0 are used
for read/write to 8279.
• It has an interrupt request line IRQ, for interrupt driven data
transfer with processor.
• The RESET signal sets the 8279 in 16-character display with two
-key lockout keyboard modes.
Block diagram of 8279
 Pin details

• A0: Selects data (0) or control/status (1) for

reads and writes between micro and 8279.
Output that blanks the displays.
• CLK: Used internally for timing. Max is 3 MHz.

• CN/ST: Control/strobe, connected to the

control key on the keyboard.
• Chip select that enables programming,
reading the keyboard, etc.
• DB7-DB0: Consists of bi-directional pins that
connect to data bus on microprocessor.
 Pin details
• IRQ: Interrupt request, becomes 1 when a key is
pressed, data is available.
• OUT A3-A0/B3-B0: Outputs that sends data to the most
significant/least significant nibble of display.

• : Connects to micro's IORC or RD signal, reads

data/status registers.
• RESET: Connects to system RESET.
• RL7-RL0: Return lines are inputs used to sense key
depression in the keyboard matrix.
•Shift: Shift connects to Shift key on keyboard.
• SL3-SL0: Scan line outputs scan both the keyboard and
displays.
Control Word Description:
Control Word Description:

First three bits given below select one of 8 control registers

(opcode).

 000DDMMM
Mode set: Opcode 000.
DD sets displays mode.
MMM sets keyboard mode.

DD field selects either:

• 8- or 16-digit display
• Whether new data are entered to
the rightmost or leftmost display
position.
Control Word Description:
MMM field:

MMM

• Encoded Mode: SL outputs are active-high, follow binary bit

pattern 0-7 or 0-15 depending on 8 or 16 digit display.
• Decoded Mode: SL outputs are active-low (only one of the four
outputs will be low at any time).Pattern output: 1110, 1101, 1011,
0111.