Introduction To Verilog

Verilog HDL Introduction
1 R V College of Engineering 24/1/2014

Verilog HDL - History
 Invented by Phil Moorby & Prabhu Goel at Gateway Design
Automation Systems in 1983/84.

 Later , Cadence took full proprietary in 1990.
 In 1995, Cadence published Verilog for public domain under OVI
(Open Verilog International).

 Verilog-95 – IEEE Standard 1364-1995.
 Verilog 2001 – IEEE Standard 1364-2001.
 Verilog 2005 – IEEE Standard 1364-2005.
2  SystemVerilog – Extended from Verilog and C++.

R V College of Engineering 24/1/2014
Levels of Abstraction
Highest Level
 Verilog supports a design at 4 of Abstraction
different levels of abstraction.

Behavioral Level
Dataflow Level
Gate Level
Switch level
Lowest Level
of Abstraction
 Register Transfer Level :
A combination of Behavioral and Data flow.

Levels of Abstraction (Cont..)
 Behavioral Level :- Used to model the behavior of a design
without describing its actual hardware structure.

 Data Flow Level :- Describes the flow of data between
registers and how a design processes that data.

 Gate Level :- Describes the logic gates and the connections
between logic gates in a design.

 Switch Level :- Describes the transistors and storage nodes in a
device and the connections between :-describes them

Design Methodologies
 There are 2 types of design methodologies:
 Top-down design methodology, and
 Bottom-up design methodology.
 In a top-down design methodology, we define the top-level block
and identify the sub-blocks necessary to build the top-level block.

 In a bottom-up design methodology, we first identify the building
blocks that are available to us. We build bigger cells, using these
building blocks.

Design Methodologies (Cont..)
Top-Down Design Methodology

Design Methodologies (Cont..)
Bottom - up Design Methodology

Structure of module
module <mod name> (<port list>);

<declarations>; // input, output, inout
// wire, register, etc.
<statements>; // initial, begin, end, always
// dataflow statements
endmodule

Structure of module (Contd..)
 The <module name> is an identifier that uniquely names the
module.
 The <port list> is a list of input, inout and output ports which are
used to connect to other modules.

 The <declares> section specifies data objects as registers,
memories and wires as wells as procedural constructs such as

functions and tasks.
 The <statements> may be initial constructs, always constructs,
9 continuous assignments or instances of modules.

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EXAMPLE
module half_adder (I1, I2, O1, O2);
input I1;
input I2;
output O1;
output O2;
// Blank lines are allowed
assign 01 = I1 ^ I2;
assign O2 = I1 & I2;
endmodule

Basic Languages Concepts

Lexical Conventions
•Similar to those in C
•Verilog contains stream of tokens
•Tokens can be
–Whitespace
–Comments
–Operators
–Numbers (constants)
–Strings
–Identifiers
–Keywords –are in lowercase!!!!!

Whitespace
•Consists of
–Blank spaces, tabs and newlines
•Whitespace is ignored in Verilog EXCEPT when it separates

tokens
•White space not ignored in strings

Verilog Comments
 Verilog supports 2 type of comment syntaxes
 Single line comment start with //, and end with newline.
 Block comment, start with /*, and end with */. Block comment cannot
be nested.

Strings
•Enclosed in double quotes
•Sequence of characters
•Has to be contained in one single line –without a return

–i.e –cannot be on multiple lines
–“Hello world”
–“a/b”

Keywords
•Verilog contains keywords, which are predefined
•They are lowercase and case sensitive

Identifier
 A letter or _ can be followed by letters, digits, $ and _
 Cannot start with digit or $ sign
 Max 1024 characters
 First character cannot be digit or $ ($ is reserved for tasks)
reg value; //reg–keyword, value –identifier

input clk; //input –keyword, clk–identifier

Numbers in Verilog (i)
<size>’<radix> <value>
No
Noofof Binary
Binary 
bbor
orBB Consecutive
bits Consecutivechars
chars
bits Octal
Octal 
ooororOO 0-f,
0-f,x,x,zz
Decimal
Decimal 
ddor
orDD
Hexadecimal
Hexadecimal hhor
orHH
8’h ax = 1010xxxx
12’habc //12 bit hexadecimal number
18 Verilog HDL Basics
Numbers in Verilog (ii)
You can insert “_” for readability
12’b 000_111_010_100
12’b 000111010100 Represent the same number
Bit extension
MS bit = 0, x or z  extend this
 4’b x1 = 4’b xx_x1
 32’bz//32 bit high impedance number
 4’b10?? = 4’b10zz

Numbers in Verilog (iii)
If size is ommitted it
is inferred from the value or
takes the simulation specific number of bits or takes the
machine specific number of bits
’hc3// This is 32 bit
If radix is ommitted too .. decimal is assumed

15 = <size>’d 15

Data Types
•Value/Scalar set
•Nets
•Registers
•Vectors
•Integer, Real and Time Register
•Arrays
•Strings

Value/scalar set
A scalar quantity is a single bit

The value of this bit can be one of
0 -logic zero (false)
1 -logic one (true)
x -unknown value
z -high-impedance value, floating gate

Nets
•Nets represent connections between hardware elements
•Nets are declared with keyword wire
•One-bit values by default unless declared explicitly as
vectors
•Default value is z
•Net is not a keyword
–It represents class of data type such as wire, wand, wor,
etc

Register
•Represent data storage elements(Variable that can hold value).
•Retain value until another value is placed onto them
reg A, C; // declaration
// assignments are always done inside a procedure
A = 1;
C = A; // C gets the logical value 1
A = 0; // C is still 1
C = 0; // C is now 0
•Values of register can be changed anytime in simulation by
assigning new value to register
•Declared using keyword reg. Unlike nets, registers do not need any
drivers
•Default value is x. outputs used in always block declared as reg.
Vectors
Both nets and registers can be declared as vectors
•They are declared by using a range specifierin the declaration:
wire [msb:lsb] w1;
reg[msb:lsb] r1;
•Both msb and lsb must be constant valued expressions

wire [3:0] busA;
reg [1:4] busB;
reg [1:0] busC;
Vector assignment (by position!!)

busB[1] = busA[3];
busB = busA; 
busB[2] = busA[2];
busB[3] = busA[1];
busB[4] = busA[0];

Integer & Real Data Types
Declaration
integer i, k;
real r;
Use as registers (inside procedures)
i = 1;
r = 2.9;
k = r; // k is rounded to 3
Integers are not initialized!!
Reals are initialized to 0.0

Time
Simulation is done wrt simulation time
Time variable declared with keyword time
System function $time is invoked to get current
time time save_time;
initial
save_time = $time; //save the current simulation time

Arrays
Arrays are allowed for reg, integer, time, real,
realtime and vectorregister data types
Accessed using
<array_name>[<subscript>]
Do not confuse arrays with net or register vectors
Vector is single element that is n-bit wide
Arrays are multiple elements that are 1-bit or n-bit
wide

wire [7:0] x; // a vector
wire x [7:0]; // an array
wire [7:0] x [7:0]; // an array of vectors
wire x[7:0][7:0]; // a two dimensional array
integer count[0:7]; //array of 8 count variables
count[5] = 0; //reset 6th element of array of count
Declare memory : Mem1k*4
Reg[3:0]mem1k[0:1023]
4 bits
0
.
.
1023

Parameters
Parameters represent global constants. They are
declared with a predefined word parameter.
Parameters are constants typically used to specify the
width of variables and time delays.
module (x,y,z);
parameter N=3;
input [N:0] x;

Operators

Logical Operators
 &&  logical AND
 ||  logical OR
 !  logical NOT
Operands evaluated to ONE bit value: 0, 1 or x

Result is ONE bit value: 0, 1 or x
A = 1; A && B  1 && 0  0
B = 0; A || !B  1 || 1  1
C = x; C || B  x || 0  x

Logical Operation Example

Bitwise Operators

Reduction operators
 Key symbols: &, ~&, |, ~|, ^, ~^, ^~.
 The reduction operators are and, nand, or, nor, xor, xnor.
They take one operand and perform a bit-by next- bit
operation, starting with the two leftmost bits, giving a 1-bit
result.

Relational & Equality Operators

Shift operators
 Key symbols:
>>: right shift
<<: left shift
 The empty bits caused by shifting are filled with zeros.
a = 4’b1010;
...
d = a >> 2; // d = 0010
c = a << 1; // c = 0100
Conditional Operator
 cond_expr ? true_expr : false_expr
 A ternary operator
 Acts like a 2-to-1 mux.

Concatenation Operator
{,}: concatenation operator
 {op1, op2, ..}concatenates op1, op2, .. to single number.

Replication Operator
 {} : replication operator
 <no> { <variable/sized_number> }
 <no> is an integer.

Arithmetic Operators (i)
 +, -, *, /, %,**
Negative integers:
can be assigned negative values
different treatment depending on base specification or not

reg [15:0] regA;
integer intA;
..
intA = -12/3; // evaluates to -4

Operators
•There are of three types
–Unary -precede the operand
 a = ~b; //~ is a unary operator. b is the operand
–Binary –operators appear between two operands

 a = b && c; //&& is a binary operator. b and c are
operands
–Ternary –have two separate operators that separate three

operands
 a = cond_expr? true_expr: false_expr//?: -ternary
operator.
R V College of Engineering
42 24/1/2014
Operator Precedence
Use parentheses to
enforce your
priority

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Verilog HDL Introduction

1 R V College of Engineering 24/1/2014

Automation Systems in 1983/84.

 In 1995, Cadence published Verilog for public domain under OVI

(Open Verilog International).

 Verilog 2001 – IEEE Standard 1364-2001.

 Verilog 2005 – IEEE Standard 1364-2005.

2  SystemVerilog – Extended from Verilog and C++.

different levels of abstraction.

3 R V College of Engineering 24/1/2014

without describing its actual hardware structure.

registers and how a design processes that data.

between logic gates in a design.

device and the connections between :-describes them

 Top-down design methodology, and

 Bottom-up design methodology.

 In a top-down design methodology, we define the top-level block

and identify the sub-blocks necessary to build the top-level block.

5 R V College of Engineering 24/1/2014

Top-Down Design Methodology

6 R V College of Engineering 24/1/2014

Bottom - up Design Methodology

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module <mod name> (<port list>);

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used to connect to other modules.

memories and wires as wells as procedural constructs such as

9 continuous assignments or instances of modules.

10 R V College of Engineering 24/1/2014

11 R V College of Engineering 24/1/2014

12 R V College of Engineering 24/1/2014

•Whitespace is ignored in Verilog EXCEPT when it separates

•White space not ignored in strings

13 R V College of Engineering 24/1/2014

14 R V College of Engineering 24/1/2014

•Has to be contained in one single line –without a return

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•Verilog contains keywords, which are predefined

•They are lowercase and case sensitive

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 Cannot start with digit or $ sign

 Max 1024 characters

 First character cannot be digit or $ ($ is reserved for tasks)

reg value; //reg–keyword, value –identifier

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19 Verilog HDL Basics

If radix is ommitted too .. decimal is assumed

20 Verilog HDL Basics

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A scalar quantity is a single bit

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•Both msb and lsb must be constant valued expressions

Vector assignment (by position!!)

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26 Verilog HDL Basics

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