Digital Integrated Circuits

INTRODUCTION TO TTL
Introduction
IC digital logic families
 RTL （ Resistor-transistor logic ）
 DTL （ Diode-transistor logic ）
 TTL （ Transistor -transistor logic ）
 ECL （ Emitter-coupled logic ）
 MOS （ Metal-oxide semiconductor ）
 CMOS （ Complementary Metal-oxide
semiconductor ）
Logic Families
Transistor Transistor Logic (TTL) is one
of the most popular and widespread of
all logic families.
 Very high number of SSI and MSI devices
available in the market.
 Several number of sub-families that provide
a wide range of speed and power
consumption.
Sub families:
 74xx : The original TTL family.
 These devices had a propagation delay of 10ns
and a power consumption of 10mW, and they
were introduced in the early 60’s.
Logic Families
Sub families:
 74Hxx : High speed.
 Speed was improved by reducing the
internal resistors. Note that this
improvement caused an increase in the
power consumption.
 74Lxx : Low power.
 Power consumption was improved by
increasing the internal resistances, and
the speed decreased.
Logic Families
Sub families:
 74Sxx : Schottky.
 The use of Schottky transistors improved
the speed. The power dissipation is less
than the 74Hxx sub-family.
 74LSxx : Low power Schottky.
 Uses Schottky transistors to improve
speed. High internal resistances improves
power consumption.
Logic Families
Sub families:
 74ASxx : Advanced Schottky.
 Twice as fast as 74Sxx with
approximately the same power
dissipation.
 74ALSxx : Advanced Low power
Schottky.
 Lower power consumption and higher
speed than 74LSxx .
 74Fxx : Fast.
 Performance is between 74ASxx and
74ALSxx.
Feature
The feature to be concerned of IC logic families:
 fan-out
 The no. of standard loads can be connected to the output of
the gate without degrading its normal operation
 Sometimes the term loading is used
 Power dissipation
 The power needed by the gate
 Expressed in mW
 Propagation delay
 The average transition-delay time for the signal to propagate
from input to output when the binary signal changes in value
 Noise margin
 The unwanted signals are referred to as noise
 Noise margin is the maximum noise added to an input signal
of a digital circuit that does not cause an undesirable change
in the circuit output
 Computing fan-out ( High-level
output)

Copyright ©2006 by Pearson Education, Inc.

William Kleitz Upper Saddle River, New Jersey 07458
Digital Electronics with VHDL, Quartus® All rights reserved.
II Version
 Computing fan-out ( Low-level output)

Copyright ©2006 by Pearson Education, Inc.

William Kleitz Upper Saddle River, New Jersey 07458
Digital Electronics with VHDL, Quartus® All rights reserved.
II Version
Power dissipation
I CCH  I CCL
I CC (avg ) 
2
PD (avg )  I CC (avg )  VCC

For standard TTL

I CCH  1mA, I CCL  3mA
PD (avg )  ?
Total PD (avg ) in IC 7400  ?
Propagation delay
50% VH 50% VH

50% VH 50% VH

For standard TTL t PHL  7 ns, t PLH  11ns

t P (avg )  ?
Noise margin
Noise margin

High-state noise margin=0.4

Low-state noise margin=0.4
Transistor-Transistor Logic (TTL)

The original basic TTL gate was a slight

improvement over the DTL gate.
There are several TTL subfamilies or series of the
TTL technology.
Eight TTL series appear in Table 10-2.
Has a number start with 74 and follows with a suffix
that identifies the series type, e.g 7404, 74S86,
74ALS161.
Three different types of output configurations:
 1. open-collector output
 2. Totem-pole output
 3. Three-state (or tristate) output
 T3
T2
T1
T4

Because of TOTEM –POLE arrangement (active

pull-up) of T-3 & T-4 Resistance offered at output
is LOW which results in fast transitions from 10 or
01
A B Q-1 Q-2 Q-3 Q-4 Y
0 0 ON OFF ON OFF 1
0 1 ON OFF ON OFF 1
1 0 ON OFF ON OFF 1
1 1 OFF ON OFF ON 0
Open-collector TTL Gate
To overcome the current
drain problem we use
OPEN COLLECTOR TTL
GATEES
A presentation by-
Pranav Naik
Rahul Kulkarni
Mandar Joshi