Figure 6-1 Representation of signed numbers in sign-magnitude form.

© 2007 Pearson Education, Inc.

Digital Systems: Principles and Applications, 10e Pearson Prentice Hall
By Ronald J. Tocci, Neal S. Widmer, and Gregory L. Moss Upper Saddle River, NJ 07458
Figure 6-2 Representation of signed numbers in the 2’s-complement system.

© 2007 Pearson Education, Inc.

Digital Systems: Principles and Applications, 10e Pearson Prentice Hall
By Ronald J. Tocci, Neal S. Widmer, and Gregory L. Moss Upper Saddle River, NJ 07458
Figure 6-3 A four-bit number circle.

© 2007 Pearson Education, Inc.

Digital Systems: Principles and Applications, 10e Pearson Prentice Hall
By Ronald J. Tocci, Neal S. Widmer, and Gregory L. Moss Upper Saddle River, NJ 07458
Figure 6-4 Functional parts of an ALU.

© 2007 Pearson Education, Inc.

Digital Systems: Principles and Applications, 10e Pearson Prentice Hall
By Ronald J. Tocci, Neal S. Widmer, and Gregory L. Moss Upper Saddle River, NJ 07458
Figure 6-5 Typical binary addition process.

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Digital Systems: Principles and Applications, 10e Pearson Prentice Hall
By Ronald J. Tocci, Neal S. Widmer, and Gregory L. Moss Upper Saddle River, NJ 07458
Figure 6-6 Block diagram of a five-bit parallel adder circuit using full adders.

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Digital Systems: Principles and Applications, 10e Pearson Prentice Hall
By Ronald J. Tocci, Neal S. Widmer, and Gregory L. Moss Upper Saddle River, NJ 07458
Figure 6-7 Truth table for a full-adder circuit.

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Digital Systems: Principles and Applications, 10e Pearson Prentice Hall
By Ronald J. Tocci, Neal S. Widmer, and Gregory L. Moss Upper Saddle River, NJ 07458
Figure 6-8 Complete circuitry for a full adder.

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Digital Systems: Principles and Applications, 10e Pearson Prentice Hall
By Ronald J. Tocci, Neal S. Widmer, and Gregory L. Moss Upper Saddle River, NJ 07458
Figure 6-9 K mappings for the full-adder outputs.

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Digital Systems: Principles and Applications, 10e Pearson Prentice Hall
By Ronald J. Tocci, Neal S. Widmer, and Gregory L. Moss Upper Saddle River, NJ 07458
Figure 6-10 (a) Complete four-bit parallel adder with registers; (b) signals used to add binary numbers from memory and store their sum
in the accumulator.

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Digital Systems: Principles and Applications, 10e Pearson Prentice Hall
By Ronald J. Tocci, Neal S. Widmer, and Gregory L. Moss Upper Saddle River, NJ 07458
Figure 6-11 (a) Block symbol for the 74HC283 four-bit parallel adder; (b) cascading two 74HC283s.

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Digital Systems: Principles and Applications, 10e Pearson Prentice Hall
By Ronald J. Tocci, Neal S. Widmer, and Gregory L. Moss Upper Saddle River, NJ 07458
Figure 6-12 Parallel adder used to add and subtract numbers in 2’s-complement system.

© 2007 Pearson Education, Inc.

Digital Systems: Principles and Applications, 10e Pearson Prentice Hall
By Ronald J. Tocci, Neal S. Widmer, and Gregory L. Moss Upper Saddle River, NJ 07458
Figure 6-13 Parallel adder used to perform subtraction (A – B) using the 2’s-complement system. The bits of the subtrahend (B) are
inverted, and C0 = 1 to produce the 2’s complement.

© 2007 Pearson Education, Inc.

Digital Systems: Principles and Applications, 10e Pearson Prentice Hall
By Ronald J. Tocci, Neal S. Widmer, and Gregory L. Moss Upper Saddle River, NJ 07458
Figure 6-14 Parallel adder/subtractor using the 2’s-complement system.

© 2007 Pearson Education, Inc.

Digital Systems: Principles and Applications, 10e Pearson Prentice Hall
By Ronald J. Tocci, Neal S. Widmer, and Gregory L. Moss Upper Saddle River, NJ 07458
Figure 6-15 (a) Block symbol for 74LS382/HC382 ALU chip; (b) function table showing how select inputs (S) determine what
operation is to be performed on A and B inputs.

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Digital Systems: Principles and Applications, 10e Pearson Prentice Hall
By Ronald J. Tocci, Neal S. Widmer, and Gregory L. Moss Upper Saddle River, NJ 07458
Figure 6-16 Two 74HC382 ALU chips connected as an eight-bit adder.

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Digital Systems: Principles and Applications, 10e Pearson Prentice Hall
By Ronald J. Tocci, Neal S. Widmer, and Gregory L. Moss Upper Saddle River, NJ 07458
Figure 6-17 Parallel adder/subtractor circuit.

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Digital Systems: Principles and Applications, 10e Pearson Prentice Hall
By Ronald J. Tocci, Neal S. Widmer, and Gregory L. Moss Upper Saddle River, NJ 07458
Figure 6-18 An Altera graphic description file of an eight-bit ALU.

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Digital Systems: Principles and Applications, 10e Pearson Prentice Hall
By Ronald J. Tocci, Neal S. Widmer, and Gregory L. Moss Upper Saddle River, NJ 07458
Figure 6-19 Four-bit parallel adder.

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Digital Systems: Principles and Applications, 10e Pearson Prentice Hall
By Ronald J. Tocci, Neal S. Widmer, and Gregory L. Moss Upper Saddle River, NJ 07458
Figure 6-20 Block symbol generated by Altera MAX+PLUS.

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Digital Systems: Principles and Applications, 10e Pearson Prentice Hall
By Ronald J. Tocci, Neal S. Widmer, and Gregory L. Moss Upper Saddle River, NJ 07458
Figure 6-21 AHDL adder.

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Digital Systems: Principles and Applications, 10e Pearson Prentice Hall
By Ronald J. Tocci, Neal S. Widmer, and Gregory L. Moss Upper Saddle River, NJ 07458
Figure 6-22 VHDL adder.

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Digital Systems: Principles and Applications, 10e Pearson Prentice Hall
By Ronald J. Tocci, Neal S. Widmer, and Gregory L. Moss Upper Saddle River, NJ 07458
Figure 6-23 An n-bit adder/subtractor description in AHDL.

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Digital Systems: Principles and Applications, 10e Pearson Prentice Hall
By Ronald J. Tocci, Neal S. Widmer, and Gregory L. Moss Upper Saddle River, NJ 07458
Figure 6-24 An n-bit adder/subtractor description in VHDL.

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Digital Systems: Principles and Applications, 10e Pearson Prentice Hall
By Ronald J. Tocci, Neal S. Widmer, and Gregory L. Moss Upper Saddle River, NJ 07458
Figure 6-25 Single-bit full adder in VHDL.

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Digital Systems: Principles and Applications, 10e Pearson Prentice Hall
By Ronald J. Tocci, Neal S. Widmer, and Gregory L. Moss Upper Saddle River, NJ 07458
Figure 6-26 Use of the VHDL GENERATE statement.

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Digital Systems: Principles and Applications, 10e Pearson Prentice Hall
By Ronald J. Tocci, Neal S. Widmer, and Gregory L. Moss Upper Saddle River, NJ 07458
Figure 6-27 Problem 6-20.

© 2007 Pearson Education, Inc.

Digital Systems: Principles and Applications, 10e Pearson Prentice Hall
By Ronald J. Tocci, Neal S. Widmer, and Gregory L. Moss Upper Saddle River, NJ 07458