MOS Capacitance

Content
 Gate Capacitance
• Channel capacitance
• Overlap capacitance
 Junction Capacitance
 Capacitance equations
 Examples
MOSFET Capacitances
 Gate Capacitance
• Due to Gate and Oxide layer(SiO2)
• Total Gate Capacitance(CT) is sum of
a) Gate to source capacitance(Cgs)
b) Gate to Drain Capacitance(Cgd)
c) Gate to Body Capacitance(Cgb)
1. Channel capacitance
• Gate and the channel act as two conducting
plates and oxide layer acts as a dielectric.
 Cutoff region
• |Vgs | < |Vth |
• Channel is not formed.
• Depletion mode
• Cgs= 0, Cgd=0
• Cgb= Cox*WL = Co
Linear Region
• |Vgs| > |Vth|
• Channel Starts forming
• Cgs = Co/2
• Cgd = Co/2
• Cgb = 0
Saturation Region
• Channel narrows
• Cgs = (2*Co)/3, Cgd = 0, Cgb = 0
C-V Characteristics
 2. Overlap Capacitance
• Source and Drain tend to
extend below the oxide by
an amount Xd called
diffusion.
• Effective length of channel
therefore decreases.
• Cgso = Cgdo = Cox*Xd* W = Co*W
 Practical Capacitance equation
Operatio
n Cgs Cgd Cgb CT
Region

Cut Off CoxWLov CoxWLov CoxWLeff CoxWLeff +

2CoxWLov

Linear 0.5Co+CoxW 0.5Co+Cox 0 Co+ 2CoxWLov

Lov WLov

Saturatio 0.67Co+Cox 0 0 0.67Co+CoxWLov

n WLov
 Juction Capacitance
1. Source to Body junction capacitance(Csb)
2. Drain to Body junction capacitance(Cdb)
• The n+ regions form a number of planar pn-
junctions with the surrounding p-type substrate.
 Junction Capacitance(Cont..)
• The source-substrate and drain-substrate junctions are
reverse biased under normal operating conditions.
• The amount of junction capacitance is a function of
applied terminal voltages

Vgs = 0 Vgd
+ g +
- -
s d
n+ n+

p-type body
b
 Equation for Junction capacitance
• A - junction area.  Si q  N A N D  1 
C j0    
• Cj0 - Zero bias capacitance 2  N A  N D   0 
• NA and ND - n-type and p-type
doping densities respectively.
• V - Negative reverse bias AC j 0
voltage. C j (V )  m
 V 
1  
• The value of the junction  0 
capacitance ultimately depends
on the external bias voltage(V)
applied across the pn-junction.
References
• https://nptel.ac.in/courses/108107129/
Unit 1 – MOS parasitic and SPICE Model
 Quick Revision(Gate Capacitance)
• The gate-to-source capacitance is actually the gate-to-channel capacitance
seen between the gate and the source terminals.
• The gate-to-drain capacitance is actually the gate-to-channel capacitance
seen between the gate and the drain terminals.
• In Cut-off mode the surface is not inverted and there is no conducting
channel linking the surface to the source and to the drain.
• The gate-to-source and gate-to-drain capacitances are both equal to zero
(Cgs=Cgd=0).
• The gate-to-substrate capacitance can be approximated by: Cgb=CoxWL
• In linear mode the inverted channel extends across the MOSFET between
the source and drain. This conducting inversion layer on the surface
effectively shields the substrate from the gate electric field making it
Cgb=0.
 Quick Revision(Cont..)
• In linear mode the distributed gate-to-channel capacitance
maybe viewed as being shared equally between the source and
the drain leading to: Cgs=Cgd=0.5CoxWL
• If the MOSFET is operating in saturation mode the inversion
layer on the surface does not extend to the drain, but is pinched
off.
• The gate-to-drain capacitance in therefore zero (Cgd=0).
• The source is however still linked to the conducting channel. It
shields the gate from the channel leading to Cgb of zero.
• The distributed gate-to-channel capacitance as seen between
the gate and the source is approximated by: Cgs2/3CoxWL.