Advanced

Microprocessor
Designs

Lecture 10

Few Important Concepts

related to Advanced
Processors
 An overview of CPU design

• We can divide the design of our CPU into three parts:

– The datapath does all of the actual data processing.
– An instruction set is the programmer’s interface to CPU.
– A control unit uses the programmer’s instructions to tell the
datapath what to do.

• Other Resources:
– An ALU does computations.
– A limited set of registers serve as fast temporary storage.
– A larger, but slower, random-access memory is also available.

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 What is CPU?: A Sequential Circuit

ALU

Registers

• A processor is just one big sequential circuit.

– Some registers are used to store values, which form the
state.
– An ALU performs various operations on the data stored in
the registers.

• Fundamentally, the processor is just moving data between

registers, possibly with some ALU computations

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 Register Transfer Language (Review)
• RTL is a kind of intermediate representation (IR) that is very close to
assembly language. It is used to describe data flow at the register -
transfer level of an architecture.

• Two-character names denote registers, such as R0, R1, DR, or SA.

• Arrows indicate data transfers. To copy the contents of the source

register R2 into the destination register R1 in one clock cycle:

R1  R2

• A conditional transfer is performed only if the Boolean condition in

front of the colon is true. To transfer R3 to R2 when K = 1:

K: R2  R3

• Multiple transfers on the same clock cycle are separated by commas.

R1  R2, K: R2  R3
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 Register Transfer Language (Review)
• We can apply arithmetic operations to registers.

R1  R2 + R3
R3  R1 - 1

• Logical operations are applied bitwise. AND and OR are denoted with
special symbols, to prevent confusion with arithmetic operations.

R2  R1  R2 bitwise AND
R3  R0  R1 bitwise OR

• Lastly, we can shift registers.

R2  sl R1 left shift
R2  sr R1 right shift

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 Block Symbols for Registers
Load

n
Data input

n R0
Data output

• Block diagram is representing an n-bit register.

• There is a data input and a load input.

– When Load = 1, the data input is stored into the register.
– When Load = 0, the register will keep its current value.

• The register’s contents are always available on the output lines,

regardless of the Load input.

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 Register File

• Modern processors have a D

number of registers grouped n
together in a Register File.
D data
WR Write
• Much like words stored in a
k
RAM, individual registers are DA D address

identified by an address. Register File

AA k A address B address k BA
• Here is a block symbol for a
k
2 x n register file. A data B data

– Register addresses are k n n

bits long, so there are 2k
registers. A B
– Each register holds an n-
bit word, so the data
inputs and outputs are n
bits wide.

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 Accessing the Register File
• Normally, two registers can
be read at once by supplying
D
the AA and BA inputs. The
data appears on the A and B n

outputs.
D data
WR Write
• You can write to a register by DA
k
D address
using the DA and D inputs,
and setting WR = 1. Register File

k k
AA A address B address BA
• These are registers so there
must be a clock signal, not A data B data

shown here. n n
– We can read from the
register file at any time. A B

– Data is written only on

the positive edge of the
clock.

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 What’s Inside the Register File
• Here’s a 4 x n register file. (We’ll assume a 4 x n register file for all
our examples.)
n

n n

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 The All-Important ALU
• General block symbol for the ALU:
– A and B are two n-bit numeric inputs.
– FS is an m-bit function select code, which picks one of 2 m functions.
– The n-bit result is called F.
– Several status bits provide more FS Operation
information about the output F: 00000 F = A
00001 F = A + 1
• V = 1 in case of signed overflow.
00010 F = A + B
• C is the carry out. 00011 F=A+B+1
• N = 1 if the result is negative. 00100 F = A + B’
• Z = 1 if the result is 0. 00101 F = A + B’ + 1
00110 F=A–1
00111 F=A
n n
01000 F = A  B (AND)
A B 01010 F= A  B (OR)
m FS 01100 F= AB
ALU 01110 F= A’
V
C
N
10000 F= B
Z 10100 F= sr B (shift right)
F
11000 F= sl B (shift left)
n 10
 Datapath

• Here is the most basic datapath. D data

WR Write
2
DA D address
– The ALU’s two data inputs come
from the register file. Register File

2 2
AA A address B address BA
– The ALU computes a result, which
A data B data
is saved back to the registers.
n n

A B
• WR, DA, AA, BA and FS are control 5
FS FS
signals. Their values determine the
exact actions taken by the datapath— V
ALU
which registers are used and for what C
N
operation. n Z
F

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 An Example Computation
• Let’s look at the proper control signals
for the operation below: D data
WR Write
R0  R1 + R3 1
DA D address
00
Register File
• Set AA = 01 and BA = 11. This causes
the contents of R1 to appear at A AA A address B address BA
data, and the contents of R3 to 01 11

appear at B data. A data B data

• Set the ALU’s function select input A B

FS = 00010 (A + B). FS FS
00010
ALU
V
• Set DA = 00 and WR = 1. On the next C
positive clock edge, the ALU result N
Z
(R1 + R3) will be stored in R0. F

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 Total Number of Required Registers ?

• Four registers isn’t a lot. What if we D data

need more storage? WR Write

DA D address

• Who exactly decides which registers Register File

are read and written and which ALU
function is executed? AA A address B address BA

A data B data

A B

FS FS

ALU
V
C
N
Z
F

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 We can access RAM also
• Here’s a way to connect RAM n
into our existing datapath.
D data
WR Write
• To write to RAM, we must give DA D address
an address and a data value. Register File

AA A address B address BA
• These will come from the A data B data RAM
registers. We connect A data n
n
ADRS
DATA OUT
to the memory’s ADRS input, +5V CS
and B data to the memory’s FS FS
A B MW
1
WR

DATA input. V ALU

C
N
Z
• Set MW = 1 to write to the F
RAM. (It’s called MW to n

distinguish it from the WR D0 n

Q D1
write signal on the register S MD
file.)

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 R3  M[R0]
• AA should be set to 00, to read n
register R0.
• The value in R0 will be sent to 1
WR Write
D data

the RAM address input, so DA D address

M[R0] appears as the RAM 11
Register File
output OUT. AA A address B address BA
• MD must be 1, so the RAM 00
A data B data RAM
output goes to the register file. n ADRS
n
• To store something into R3, +5V
DATA
CS
OUT

we’ll need to set DA = 11 and A B MW WR

FS FS 0
WR = 1. V ALU
• MW should be 0, so nothing is C
N
accidentally changed in RAM. Z
F
• Here, we did not use the ALU n
(FS) or the second register file D0 n
output (BA). Q D1
S MD
1

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 R3  R3 + 1
• AA = 11, so R3 is read from the n
register file and sent to the
ALU’s A input. 1 D data
WR Write
• FS needs to be 00001 for the DA D address
operation A + 1. Then, R3 + 1 11
Register File
appears as the ALU output F. AA A address B address BA
• If MD is set to 0, this output 11
A data B data RAM
will go back to the register file. n ADRS
n
• To write to R3, we need to +5V
DATA
CS
OUT

make DA = 11 and WR = 1. 00001 A B MW WR

FS FS 0
• Again, MW should be 0 so the V ALU
RAM isn’t inadvertently C
N
changed. Z
F
• We didn’t use BA. n

D0 n
Q D1
S MD
0

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 Constant in

D data
• One last refinement is the WR Write
addition of a Constant input. DA D address
Register File

• The modified datapath is AA A address B address BA

shown on the right, with one A data B data
extra control signal MB. Constant
MB

• It provides an easy way to S D1 D0

Q RAM
initialize a register or ADRS
memory location with some +5V
DATA
CS
OUT

arbitrary number. FS FS
A B MW WR

V
C ALU
N
Z
F

D0
Q D1
S MD

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Thank You

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