Faculty of Mechanical Engineering: Jimma Institute of Technology

Faculty of
Mechanical Engineering
Jimma Institute of Technology
MEng 5271 Introduction to Mechatronics
Thursday, December 31, 2020 CHAPTER-5 DIGTAL LOGICS 1

Chapter-3
Building Blocks
is not required
for Final Exam

Chapter-4
Digital Logics
Digital Logics
Most of the control systems involve digital signals where
there are only two possible signal levels.
Digital circuitry is the basis of digital computers and
microprocessor controlled systems.
With digital control we might, for example,
have the water input to the domestic washing
machine switched on
if we have both the door to the machine closed and
a particular operating cycle has been selected.

Digital Logics
There are two input signals which are either yes or no
signals and an output signal which is a yes or no signal.
The controller is here programmed to only give a yes output
if both the input signals are yes, i.e. input A and input B are
both 1 then there is an output of 1.
Such an operation is said to be controlled by a logic gate,
in this example, it is an AND gate.

Combinational Logics
The term combinational logic is used for the combining of
two or more basic logic gates to form a required function.
For example, a requirement might be that a buzzer sounds
in a car if the key is in the ignition and a door is opened or
if the headlights are on and the driver's door is opened.
Combinational logic depends only on the values of the
inputs at a particular instant of time.

Sequential Logics
Sequential logic digital circuitry is used to exercise control in
a specific sequence dictated by a control clock or enable-
disable control signals.
These are combinational logic circuits with memory.
Thus the timing or sequencing history of the input signals
plays a part in determining the output.

Logic Gates
1. AND gate
Suppose we have a gate giving a high output only when
both input A and input B are high; for all other conditions it
gives a low output.
This is an AND logic gate.
We can visualize the AND gate as an electric circuit
involving two switches in series (Figure 5.I (a)).
Only when switch A and switch B are closed is there a
current.

1. AND gate
Different sets of standard circuit symbols for logic gates
have been used, with the main form being that originated
in the United States.
An international standard form (IEEE/ANSI), however, has
now been developed; this removes the distinctive shape and
uses a rectangle with the logic function written inside it.
Figure 5.I (b) shows the US form of symbol used for an AND gate and
(c) shows the new standardized form, the & symbol indicating AND.

1. AND gate
Figure 5.I (b) shows the US form of symbol used for an AND
gate and (c) shows the new standardized form, the &
symbol indicating AND.
As illustrated in the figure, we can express the relationship
between the inputs and the outputs of an AND gate in the
form of an equation, termed a Boolean equation.
The Boolean equation for AND gate is written as: A.B = Q

1. AND gate
An example of an AND gate is an interlock control system
for a machine tool such that if the safety guard is in place
and gives a 1 signal and the power is on, giving a 1 signal,
then there can be an output, a 1 signal, and the machine
operates.
Another example is a burglar alarm in which it gives an
output, the alarm sounding, when the alarm is switched on
and when a door is opened to activate a sensor.

1. AND gate – Truth table
The relationships between inputs to a logic gate and the
outputs can be tabulated in a form known as a truth table.
This specifies the relationships between the inputs and
outputs.
Thus for an AND gate with inputs A and B and a single
output Q, we will have a I output when, and only when,
A=1 and B = 1.
All other combinations of A and
B will generate a 0 output.
We can thus write
the truth table as

1. AND gate - with two digital inputs
Consider what happens when we have two digital inputs
which are functions of time, as in Figure 5.2.
Such a figure is termed an AND gate timing diagram.
There will only be an output from the AND gate when each
of the inputs is high and thus the output is as shown in the
figure.

2. OR gate
An OR gate with inputs A and B gives an output of a 1 when
A or B is 1.We can visualize such a gate as an electric circuit
involving two switches in parallel (Figure 5.3(a)).
When switch A or B is closed, then there is a current.
OR gates can also have more than two inputs.
We can thus write
the truth table as

2. OR gate
We can write the Boolean equation for an OR gate as A+B=Q
The symbols used for an OR gate are shown in Figure 5.3(b);
the use of a greater than or equal to I sign to depict OR arises
from the OR function being true if at least more than one
input is true. Figure 5.3(c) shows a timing diagram.
We can thus write
the truth table as

3. NOT gate
A NOT gate has just one input and one output, giving a 1 output
when the input is 0 and a 0 output when the input is 1.
The NOT gate gives an output which is the inversion of the input
and is called an inverter.
Figure 5.4(a) shows the symbols used for a NOT gate.
The 1 representing NOT actually symbolizes logic identity, i.e. no
operation, and the inversion is depicted by the circle on the
output.
Thus if we have a digital input which varies with time, as in
Figure 5.4(b), the out variation with time is the inverse.

3. NOT gate
The following is the truth table for the NOT gate:
The Boolean equation describing the NOT gate is: Ȃ = Q

A bar over a symbol is used to indicate that the inverse, or
complement, is being taken; thus the bar over the A indicates
that the output Q is the inverse value of A.

4. NAND gate
The NAND gate can be considered as a combination of an AND
gate followed by a NOT gate (Figure 5.5(a)).
Thus when input A is 1 and input B is 1, there is an output of 0,
all other inputs giving an output of 1.
The NAND gate is just the AND gate truth table with the
outputs inverted.

4. NAND gate
An alternative way of considering the gate is as an AND gate
with a NOT gate applied to invert both the inputs before they
reach the AND gate.
Figure 5.5(b) shows the symbols used for the NAND gate, being
the AND symbol followed by the circle to indicate inversion.

4. NAND gate
The NAND gate is just the AND gate truth table
with the outputs inverted.
The following is the truth table for NAND gate.

The Boolean equation describing the NAND gate is shown in figure
5.5(c), it also shows the output that occurs for a NAND gate when its
two inputs are digital signals which vary with time.
There is only a low output when both the inputs are high.

5. NOR gate
The NOR gate can be considered as a combination of an OR gate
followed by a NOT gate (Figure 5.6(a)).
Thus when input A or input B is 1 there is an output of 0.
It is just the OR gate with the outputs inverted.
An alternative way of considering the gate is as an OR gate with a
NOT gate applied to invert both the inputs before they reach the
OR gate.

5. NOR gate
Figure 5.6(b) shows the symbols used for the NOR gate; it is the
OR symbol followed by the circle to indicate inversion.
The Boolean equation for the NOR gate is
Figure 5.6(c) shows its timing diagram:
The following is the truth table
for the NOR gate:

6. XOR gate
The EXCLUSIVE-OR gate (XOR) can be considered to be an OR
gate with a NOT gate applied to one of the inputs to invert it
before the inputs reach the OR gate (Figure 5.7(a)).
Alternatively it can be considered as an AND gate with a NOT
gate applied to one of the inputs to invert it before the inputs
reach the AND gate.

6. XOR gate
The symbols are shown in Figure 5.7(b); the =1 depicts that the
output is true if only one input is true.
Figure 5.7(c) shows a timing diagram:
The following is the truth table for XOR gate:

Combining Gates
It might seem that to make logic systems we require a
range of gates.
An example of the combination of three NOR gates
is shown in Figure 5.8.
The result is the same as an AND gate.

Combining Gates
It might seem that to make logic systems we require a
range of gates.
An example of the combination of three NAND gates is
shown in Figure 5.9.
then we would obtain a truth table the same as a OR gate

Combining Gates: IC7408
Logic gates are available as integrated circuits. For example,
Figure 5.10(a) shows the gate systems available in integrated
circuit 7408; it has four two-input AND gates and is supplied in a
14-pin package.
Power supply connections are made to pins 7 and 14, these
supplying the operating voltage for all the four AND gates.
In order to indicate at which end of the package pin 1 starts, a
notch is cut between pins 1 and 14.

Combining Gates: IC7402
Logic gates are available as integrated circuits.
For example, Figure 5.10(b) shows the gate systems
available in integrated circuit 7402.
This has four two-input NOR gates in a 14-pin package,
power connections being to pins 7 and 14.

Application of
Logic Gates
Applications of Logic Gates
1. Parity Generators
2. Digital Comparators
3. Coder
4. Flip-Flop
5. JK Flip-Flop
6. D Flip-Flop
7. Registers
8. 555 Timer

Figure below shows a logic gate circuit that could be used to
determine and add the appropriate parity bit.
A single bit is added to each code block to force the number
of ones in the block, including the parity bit, to be an odd
number if odd parity is being used or an even number if even
parity is being used.

The system employs XOR gates; with an XOR gate if all the
inputs are 0 or all are 1 the output is 0, and if the inputs
are not equal the output is a 1.
Pairs of bits are checked and an output of 1 given if they
are not equal.
If odd parity is required the bias bit is 0; if even parity it is 1.
The appropriate bias bit can then be added to the signal for
transmission.

A digital comparator is used to compare two digital words to
determine if they are exactly equal.
The two words are compared bit by bit and a 1 output given if
the words are equal.
To compare the equality of two bits, an XOR gate can be
used; if the bits are both 0 or both 1 the output is 0, and if
they are not equal the output is 1.

To obtain a 1 output when the bits are the same we need to
add a NOT gate, this combination of XOR and NOT being
termed an XNOR gate.
To compare each of the pairs of bits in two words we need an
XNOR gate for each pair.
If the pairs are made up of the same bits then the output
from each XNOR gate is a 1.

We can then use an AND gate to give a 1 output when all
the XNOR outputs are ones.
Figure 5.12 shows the digital comparator.
Digital comparators are available as integrated circuits and
can generally determine not only if two words are equal
but which one is greater than the other.

3. Coder
Figure 5.13 shows a simple system by which a controller can send
a coded digital signal to a set of traffic lights so that the code
determines which light, red, amber or green, will be turned on.
To illuminate the red light we might use the transmitted signal A
= 0, B = 0, for the amber light A = 0, B = 1 and for the green light
A = 1, B = 0.
We can switch on the lights using these codes by using three
AND gates and two NOT gates.

Sequential Logic
In combinational logic systems the output is determined by the
combination of the input variables at a particular instant of time.
For example, if input A and input B occur at the same time then an
AND gate gives an output.
The output does not depend on what the inputs previously were.
Where a system requires an output which depends on earlier
values of the inputs, a sequential logic system is required.

Sequential Logic
The main difference between a combinational logic system and a
sequential logic system is that the sequential logic system must
have some form of memory.
Figure 5.19 shows the basic form of a sequential logic system.
The combinational part of the system accepts logic signals from
external inputs and from outputs from the memory.
The combinational system then operates on these inputs to
produce its outputs.
The outputs are thus a function of both its external inputs and the
information stored in its memory.

4. Flip-Flop
The flip-flop is a basic memory element which is made up of
an assembly of logic gates and is a sequential logic device.
There are a number of forms of flip-flops.
Figure 5.20 (a) shows one form, the SR (set-reset) flip-flop,
involving NOR gates.

4. Flip-Flop
If initially we have both outputs 0 and S = 0 and R = 0, then
when we set and have S change from 0 to 1, the output from
'OR gate 2 will become 0.
This will then result in both the inputs to OR gate 1 becoming 0
and so its output becomes 1.
This feedback acts as an input to NOR gate 2 which then has
both its inputs at I and results in no further change.

4. Flip-Flop
Now if S changes from 1 to 0, the output from NOR gate 1
remains at 1 and the output from NOR gate 2 remains at 0.
There is no change in the outputs when the input S changes
from 1 to 0. It will remain in this state indefinitely if the only
changes are to S. It 'remembers' the state it was set to.
Figure 5.20(b) illustrates this with a timing diagram in which a
rectangular pulse is used as the input S.

4. Flip-Flop
If we change R from 0 to 1 when S is 0, the output from NOR gate 1
changes to 0 and hence the output from NOR gate 2 changes to 1.
The flip-flop has been reset.
A change then of R to 0 will have no effect on these outputs.
Thus when S is set to 1 and R made 0, the output Q will change to
1 if it was previously 0, remaining at 1 it was previously 1.
This is the set condition and it will remain in this condition even when
S changes to 0. When S is 0 and R is made 1 , the output Q is reset to
0 if it was previously 1 , remaining at 0 if it was previously 0.
This is the rest condition.
The output Q that occurs at a particular time will depend on the
inputs S and R and also the last value of the output.

SR Flip-Flop Alarm Circuit
As a simple illustration of the use of a flip-flop, consider a simple
alarm system in which an alarm is to sound when a beam of light
is interrupted and remain sounding even when the beam is no
longer interrupted. Figure 5.22 shows a possible system.
A phototransistor might be used as the sensor and so connected
that when it is illuminated it gives a virtually 0 V input to S, but
when the illumination ceases it gives about 5 V input to S.

4. Flip-Flop
The following state table illustrates this:
Note that if S and R are simultaneously made equal to 1, no

stable state can occur and so this input condition is not allowed.
Figure 5.21 shows the simplified block symbol used for the SR flip-flop.

SR Flip-Flop Alarm Circuit
When the light beam is interrupted, S becomes 1 and the
output from the flip-flop becomes 1 and the alarm sounds.
The output will remain as 1 even when S changes to 0.
The alarm can only be stopped if the reset switch is
momentarily opened to produce a 5 V input to R.

Synchronous Systems
It is often necessary for set and reset operations to occur at
particular times.
With an unclocked or asynchronous system the outputs of
logic gates can change state at any time when anyone or
more of the inputs change.
With a clocked or synchronous system the exact times at
which any output can change state are determined by a
signal termed the clock signal.
This is generally a rectangular pulse train and when the
same clock signal is used for all parts of the system, outputs
are synchronized.

Synchronous Systems
Figure 5.23(a) shows the principle of a gated SR flip-flop.
The set and clock signal are supplied through an AND gate to the S
input of the flip-flop.
Thus the set signal only arrives at the flip-flop when both it and the
clock signal are 1.
Likewise the reset signal is supplied with the clock signal to the R
input via another AND gate.
As a consequence, setting and resetting can only occur at the time
determined by the clock. Figure 5.23(b) shows the timing diagram.

5. JK Flip-Flop
For many applications the indeterminate state that occurs with the SR
flip-flop when S = 1 and R = 1 is not acceptable and another form of flip-
flop is used, the JK flip-flop (Figure 5.24).
This has become a very widely used flip-flop device.

As an illustration of the use of such a flip-flop, consider the requirement
for a high output when input A goes high and then some time later B
goes high.
An AND gate can be used to determine whether two inputs are both
high; but its output will be high regardless of which input goes high first.
However, if the inputs A and B are used with a JK flip-flop, then A must be
high first in order for the output to go high when B subsequently goes high.

5. JK Flip-Flop
The following is the truth table for this flip-flop; note that
the only changes from the state table for the SR flip-flop
are the entries when both inputs are 1:

6. D Flip-Flop
The data or D flip-flop is basically a clocked SR flip-flop or a JK flip-
flop with the D input being connected directly to the S or J inputs and
via a NOT gate to the R or K inputs (Figure 5.25(a));
in the symbol for the D flip-flop this joined R and K input is labeled D.
This arrangement means that a 0 or a 1 input will then switch the
outputs to follow the input when the clock pulse is 1 (Figure 5.25(b)).
A particular use of the D flip-flop is to ensure that the output will only
take on the value of the D input at precisely defined times.
Figure 5.25(c) shows the symbol used for a D flip-flop.

6. D Flip-Flop
With the below form of D flip-flop, when the clock or enable input
goes high, the output follows the data presented at input D.
The flip-flop is said to be transparent. When there is a high-to-low
transition at the enable input, output Q is held at the data level
just prior to the transition.
The data at transition is said to be latched. D flip-flops are
available as integrated circuits.
The 7475 is an example; it contains four transparent D latches.

7. Registers
A register is a set of memory elements and is used to hold
information until it is needed.
It can be implemented by a set of flip-flops. Each flip-flop stores
a binary signal, i.e. a 0 or a 1.
Figure 5.28 shows the form a 4-bit register
can take when using D flip-flops
When the load signal is 0, no clock input
occurs to the D flip-flops and so no change
occurs to the states of the flip-flops.
When the load signal is 1, then the inputs
can change the states of the flip-flops.
As long as the load signal is 0, the flip-
flops will hold their old state values.
8. 555 Timer
The 555 timer chip is very widely used in digital circuits as it can
provide a wide variety of timing tasks. It consists of an SR flip-flop
with inputs fed by two comparators (Figure 5.29). The
comparators each have an input voltage derived from a
potentiometric chain of equal size resistors.
So comparator A has a non-
inverting voltage input of Vcc/3 and
comparator B has an inverting input
of 2 Vcc/3.
One use of a 555 timer is as a mono-
stable multi-vibrator, this being a
circuit which will generate a single
pulse of the desired time duration
when it receives a trigger signal.
Albert Einstein once
said:
“Education is
what remains
when one has
forgotten everything
he learned in
school”
Thank you

Faculty of Mechanical Engineering: Jimma Institute of Technology

Uploaded by

Copyright:

Available Formats

You might also like

Faculty of Mechanical Engineering: Jimma Institute of Technology

Uploaded by

Document Information

Original Description:

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Faculty of Mechanical Engineering: Jimma Institute of Technology

Uploaded by

Copyright:

Available Formats

Faculty of

Thursday, December 31, 2020 CHAPTER-5 DIGTAL LOGICS 1

Thursday, December 31, 2020 CHAPTER-5 DIGTAL LOGICS 2

Thursday, December 31, 2020 CHAPTER-5 DIGTAL LOGICS 4

Thursday, December 31, 2020 CHAPTER-5 DIGTAL LOGICS 5

Thursday, December 31, 2020 CHAPTER-5 DIGTAL LOGICS 6

Thursday, December 31, 2020 CHAPTER-5 DIGTAL LOGICS 7

Thursday, December 31, 2020 CHAPTER-5 DIGTAL LOGICS 9

Thursday, December 31, 2020 CHAPTER-5 DIGTAL LOGICS 10

Thursday, December 31, 2020 CHAPTER-5 DIGTAL LOGICS 11

Thursday, December 31, 2020 CHAPTER-5 DIGTAL LOGICS 12

Thursday, December 31, 2020 CHAPTER-5 DIGTAL LOGICS 13

Thursday, December 31, 2020 CHAPTER-5 DIGTAL LOGICS 14

the truth table as

Thursday, December 31, 2020 CHAPTER-5 DIGTAL LOGICS 15

We can thus write

the truth table as

Thursday, December 31, 2020 CHAPTER-5 DIGTAL LOGICS 16

Thursday, December 31, 2020 CHAPTER-5 DIGTAL LOGICS 17

The Boolean equation describing the NOT gate is: Ȃ = Q

Thursday, December 31, 2020 CHAPTER-5 DIGTAL LOGICS 18

Thursday, December 31, 2020 CHAPTER-5 DIGTAL LOGICS 19

Thursday, December 31, 2020 CHAPTER-5 DIGTAL LOGICS 20

The following is the truth table for NAND gate.

Thursday, December 31, 2020 CHAPTER-5 DIGTAL LOGICS 21

Thursday, December 31, 2020 CHAPTER-5 DIGTAL LOGICS 22

Thursday, December 31, 2020 CHAPTER-5 DIGTAL LOGICS 23

Thursday, December 31, 2020 CHAPTER-5 DIGTAL LOGICS 24

The following is the truth table for XOR gate:

Thursday, December 31, 2020 CHAPTER-5 DIGTAL LOGICS 25

The result is the same as an AND gate.

Thursday, December 31, 2020 CHAPTER-5 DIGTAL LOGICS 26

then we would obtain a truth table the same as a OR gate

Thursday, December 31, 2020 CHAPTER-5 DIGTAL LOGICS 27

Thursday, December 31, 2020 CHAPTER-5 DIGTAL LOGICS 28

Thursday, December 31, 2020 CHAPTER-5 DIGTAL LOGICS 29

Thursday, December 31, 2020 CHAPTER-5 DIGTAL LOGICS 31

Thursday, December 31, 2020 CHAPTER-5 DIGTAL LOGICS 32

Thursday, December 31, 2020 CHAPTER-5 DIGTAL LOGICS 33

Thursday, December 31, 2020 CHAPTER-5 DIGTAL LOGICS 34

Thursday, December 31, 2020 CHAPTER-5 DIGTAL LOGICS 35

Thursday, December 31, 2020 CHAPTER-5 DIGTAL LOGICS 36

Thursday, December 31, 2020 CHAPTER-5 DIGTAL LOGICS 37

Thursday, December 31, 2020 CHAPTER-5 DIGTAL LOGICS 38

Thursday, December 31, 2020 CHAPTER-5 DIGTAL LOGICS 39

Thursday, December 31, 2020 CHAPTER-5 DIGTAL LOGICS 40

Thursday, December 31, 2020 CHAPTER-5 DIGTAL LOGICS 41

Thursday, December 31, 2020 CHAPTER-5 DIGTAL LOGICS 42

Thursday, December 31, 2020 CHAPTER-5 DIGTAL LOGICS 43

Thursday, December 31, 2020 CHAPTER-5 DIGTAL LOGICS 44

Note that if S and R are simultaneously made equal to 1, no

Thursday, December 31, 2020 CHAPTER-5 DIGTAL LOGICS 45

Thursday, December 31, 2020 CHAPTER-5 DIGTAL LOGICS 46

Thursday, December 31, 2020 CHAPTER-5 DIGTAL LOGICS 47

Thursday, December 31, 2020 CHAPTER-5 DIGTAL LOGICS 48

This has become a very widely used flip-flop device.

Thursday, December 31, 2020 CHAPTER-5 DIGTAL LOGICS 49