6.5.

4 Encoders in VHDL
Behavioral VHDL program for a 8-input priority encoder
library IEEE;
use IEEE.std_logic_1164.all;

entity V74x148 is
port (
EI_L: in STD_LOGIC;
I_L: in STD_LOGIC_VECTOR (7 downto 0);
A_L: out STD_LOGIC_VECTOR (2 downto 0);
EO_L, GS_L: out STD_LOGIC
);
end V74x148;
architecture V74x148h of V74x148 is
signal EI : STD_LOGIC; --active-high version of input
signal I : STD_LOGIC_VECTOR(7 downto 0); --active-high version of inputs
signal EO, GS : STD_LOGIC; --active-high version of output
Signal A : STD_LOGIC_VECTOR(2 downto 0); --active-high version of outputs
begin
process (EI_L, I_L, EI, EO, GS, I, A)
variable j: INTEGER range 7 downto 0;
begin
EI <= not EI_L; --convert input
I <= not I_L; --convert inputs
EO <= '1'; GS <= '0'; A <= "000";
if (EI)='0' then EO <= '0';
else for j in 7 downto 0 loop
if I(j)='1' then
GS <= '1'; EO <= '0'; A <= CONV_STD_LOGIC_VECTOR(j,3);
exit;
end if;
end loop;
end if;
EO_L<=not EO; --convert output
GS_L<=not GS; --convert output
A_L<=not A; --convert outputs
end process;
end V74x148h;
 6.6 Three-state Devices

6.6.1 Three-state Buffers

The most basic three-state device is a three-state
buffer, often called a three-state driver.
 Characteristic of
Three-state Devices
Three-state devices allow multiple sources to share a single “party line,” as long
as only one
device “talks”
on the line
at a time.
 6.7 Multiplexers

 A multiplexer (MUX) is a digital switch which connects data from one of

n sources to the output.
 A number of select inputs determine which data source is connected to
the output.
D0 1Y
Multiplexer
Enable EN
s bits
2Y
Select SEL
D1
Data
b bits output
. .
D0
b bits Y . .
D1 . .
bY
n Data . Dn-1
Sources .
b bits
Dn-1
SEL EN
 6.7.1 Standard
MSI Multiplexers

8-to-1 MUX

Inputs
D0 0
D1 8:1
1
... MUX
D6
...
6 Y Output
D7 7
S2 S1 S0

Select
CBA
8-to-1
MUX
Circuit
 6.7.2 Expanding Multiplexers

 Larger multiplexers can be constructed from smaller ones.

 An 8-to-1 multiplexer can be constructed from smaller
multiplexers as shown:
I0
S2 S1 S0 Y
I1 4:1
I2 MUX 0 0 0 I0
0 0 1 I1
I3
2:1 0 1 0 I2
S1 S 0 MUX Y 0 1 1 I3
I4 1 0 0 I4
I5 4:1 1 0 1 I5
I6 MUX 1 1 0 I6
S2
I7 1 1 1 I7

S1 S 0
Expanding
Multiplexers
 6.7.3 Demultiplexers
 Demultiplexers are digital switches connect data from one input
source to one of n outputs.
 Usually implemented by using n-to-2n binary decoders where the
decoder’s enable line is used for data input of the demultiplexer.

2X4
Select Decoder
s bits Demux b bits lines One of
Select four 1-bit
One of n outputs

One of n b bits outputs

Data
Data
Sources
Input
selected
. Input Enable
. data (1bit)
b bits
1-bit 4-output demultiplexer using
a 2x4 binary decoder.
 1-to-4 Demultiplexer
Outputs

Y0 = D·S1'·S0' S1 So Y0 Y1 Y2 Y3
0 0 D 0 0 0
Y1 = D·S1'·S0
Data D demux
0 1 0 D 0 0
Y2 = D·S1·S0' 1 0 0 0 D 0
1 1 0 0 0 D
Y3 = D·S1·S0

S1 S0
select
Y0 = D·S1'·S0'
2x4
S1 Decoder Y1 = D·S1'·S0
S0 Y2 = D·S1·S0'
E Y3 = D·S1·S0

D
 Mux-Demux Application
Example

This enables sharing a single communication line among

a number of devices.
At any time, only one source and one destination can use
the communication line.
6.7.x Supplementary examples
—— Implement logic function using Multiplexers

Question: Implement the following logic functions using

8-1 multiplexer. You can use original variables and
its complement as inputs.

(1) F  AB  BC  AC
( 2) F   (0,3,5,8,10,11,14 )   x (1,6,13)
Solution
: Transform the logic function

Draw the logic circuit determine the address and input

 Transform the logic function

E
(1) F  AB  BC  AC D0
 ABC  ABC ' A' BC  AB ' C D1
D2
  (3,5,6,7) F
D3
D4
D5
Number of variables D6
equal to number of D7
A2 A1 A0
address
 Explanation ： determine
the address and input
The output function expression of 8-1 multiplexer is ：
7
Y   mi Di  A2 ' A1 ' A0 ' D0  A2 ' A1 ' A0 D1  A2 ' A1 A0 ' D2  A2 ' A1 A0 D3
i 0

 A2 A1 ' A0 ' D4  A2 A1 ' A0 D5  A2 A1 A0 ' D6  A2 A1 A0 D7

F  AB  BC  AC
 ABC  ABC ' A' BC  AB ' C
 A' B ' C '0  A' B ' C  0  A' BC '0  A' BC 1
 AB ' C '0  AB ' C 1  ABC '1  ABC 1
Comparing the 2 expressions, we know:
D0=0 D1=0 D2=0 D3=1 D4=0 D5=1 D6=1 D7=1
 Draw the logic circuit

E
D0
D0=0 D1=0 D1
D2
D2=0 D3=1 D3 F
D4
D5
D4=0 D5=1
D6
D7
D6=1 D7=1 A2 A1 A0

1 A B C
 Implement logic function using Multiplexers
(continue)

If the number of variables is greater than

number of address
(2) F ( A, B , C , D )   ( 0,3,5,8,10,11,14 )   x (1,6,13)

AB00 01 11 10
CD
00 1 1

F ( A, B , C , D )  B ' C ' D ' BC ' D 01 x 1 x

 B ' CD  ACD ' 11 1 1

10 x 1 1
 Comparing expressions

The output function expression of 8-1 multiplexer is ：

7
Y   mi Di  A2 ' A1 ' A0 ' D0  A2 ' A1 ' A0 D1  A2 ' A1 A0 ' D2  A2 ' A1 A0 D3
i 0

 A2 A1 ' A0 ' D4  A2 A1 ' A0 D5  A2 A1 A0 ' D6  A2 A1 A0 D7

F ( A, B, C , D )  B ' C ' D ' BC ' D  B ' CD  ACD '

 B ' C ' D ' BC ' D  B ' CD  BCD ' A  B ' CD ' A
 B ' C ' D '1  B ' C ' D  0  B ' CD ' A  B ' CD 1
 BC ' D '0  BC ' D 1  BCD ' A  BCD  0
 Determine the address and
input, draw up the circuit
E
1 D0
Comparing the 2 expressions, D1
D2
let BCD as address, and ： D3 F
D4
D5
D0=1 D1=0 D2=A D3=1
D6
D7
D4=0 D5=1 D6=A D7=0 A2 A 1 A 0

A
B C D
 Implement logic function using Multiplexers
(Example 2)

Question: Implement the following logic function using

4-1 multiplexer 74LS153. You can use original variables
and its complement as inputs.

F ( X ,Y , Z )   (1,2,3,4,5,6)
Solution
: Transform the logic function

Draw up the logic circuit determine the address and input

 Transform the logic function

F ( X , Y , Z )   (1,2,3,4,5,6)
XY00 01 11 10
Z
0 1 1 1
 X ' Z  X ' Y  XY ' XZ '
1 1 1 1

Number of variables is Both address and

greater than number of data input should
address be used
 Comparing expressions

The output function expression of 4-1 multiplexer is ：

3
Y  m D
i0
i i  A1 ' A0 ' D0  A1 ' A0 D1  A1 A0 ' D 2  A1 A0 D3

F ( X , Y , Z )  X ' Z  X ' Y  XY ' XZ '

 X ' YZ  X ' Y ' Z  X ' Y  XY ' XYZ ' XY ' Z '
 X ' Y ' Z  X ' Y  XY ' XYZ '
 X ' Y 'Z  X ' Y 1  XY '1  XY  Z '
 Determine the address and
input, draw up the circuit

Comparing the 2 expressions, E

Z D0
let XY as address, and ： 1 D1
F
D2
D0=Z D1=1 Z’ D3
A1 A0
D2=1 D3=Z’
X Y
 6.8 Exclusive-OR gates
and Parity Circuits
6.8.1 Exclusive-OR and Exclusive-NOR Gates
2-input XOR gates
 Like an OR gate, but excludes the case
where both inputs are 1.
X Y XY (XY)’
0 0 0 1
0 1 1 0 X Y=X’Y+XY’
1 0 1 0
1 1 0 1

 XNOR: complement of XOR

 XOR and XNOR symbols
X Y=X’Y+XY’ X’ Y’=(X’)’Y+X’(Y’)’=XY’ + X’Y

XY  X’  Y’  (X’  Y)’  (X  Y’)’

(X  Y)’  (X’  Y’)’  (X’  Y)  (X  Y’)

Gate-level XOR circuits

((X(XY)’)’)’+((Y(XY)’)’)’
= X(XY)’+Y(XY)’
= XY’+X’Y
 6.8.2 Parity Circuits
 Odd parity circuit (its output is 1 if an odd
number of its inputs are 1)
 Detects any single-bit error
 Parity tree
 Faster with balanced tree structure
6.8.6 Parity Circuits in VHDL
Behavioral VHDL for 9-input parity checker
library IEEE;
use IEEE.std_logic_1164.all;
entity parity9 is
port (
I: in STD_LOGIC_VECTOR (1 to 9);
EVEN, ODD: out STD_LOGIC );
end parity9;
architecture parity9p of parity9 is
begin
process (I)
variable p : STD_LOGIC;
begin
p := I(1);
for j in 2 to 9 loop
if I(j) = '1' then p := not p;
end if;
end loop;
ODD <= p;
EVEN <= not p;
end process;
end parity9p;
architecture parity9p of parity9 is
begin
example: I =“100110101”
process (I) I(1) … I(9)
variable p : STD_LOGIC; p j I(j) p:=not p
begin ‘1’
p := I(1);
for j in 2 to 9 loop
if I(j) = '1' then p := not p;
end if;
end loop;
ODD <= p;
EVEN <= not p;
end process;
end parity9p;
architecture parity9p of parity9 is
begin
example: I =“100110101”
process (I) I(1) … I(9)
variable p : STD_LOGIC; p j I(j) p:=not p
begin ‘1’
p := I(1); ‘1’ 2 ‘0’ --
for j in 2 to 9 loop
if I(j) = '1' then p := not p;
end if;
end loop;
ODD <= p;
EVEN <= not p;
end process;
end parity9p;
architecture parity9p of parity9 is
begin
example: I =“100110101”
process (I) I(1) … I(9)
variable p : STD_LOGIC; p j I(j) p:=not p
begin ‘1’
p := I(1); ‘1’ 2 ‘0’ --
for j in 2 to 9 loop ‘1’ 3 ‘0’ --
if I(j) = '1' then p := not p;
end if;
end loop;
ODD <= p;
EVEN <= not p;
end process;
end parity9p;
architecture parity9p of parity9 is
begin
example: I =“100110101”
process (I) I(1) … I(9)
variable p : STD_LOGIC; p j I(j) p:=not p
begin ‘1’
p := I(1); ‘1’ 2 ‘0’ --
for j in 2 to 9 loop ‘1’ 3 ‘0’ --
if I(j) = '1' then p := not p; ‘1’ 4 ‘1’ ‘0’
end if;
end loop;
ODD <= p;
EVEN <= not p;
end process;
end parity9p;
architecture parity9p of parity9 is
begin
example: I =“100110101”
process (I) I(1) … I(9)
variable p : STD_LOGIC; p j I(j) p:=not p
begin ‘1’
p := I(1); ‘1’ 2 ‘0’ --
for j in 2 to 9 loop ‘1’ 3 ‘0’ --
if I(j) = '1' then p := not p; ‘1’ 4 ‘1’ ‘0’
end if; ‘0’ 5 ‘1’ ‘1’
end loop;
ODD <= p;
EVEN <= not p;
end process;
end parity9p;
architecture parity9p of parity9 is
begin
example: I =“100110101”
process (I) I(1) … I(9)
variable p : STD_LOGIC; p j I(j) p:=not p
begin ‘1’
p := I(1); ‘1’ 2 ‘0’ --
for j in 2 to 9 loop ‘1’ 3 ‘0’ --
if I(j) = '1' then p := not p; ‘1’ 4 ‘1’ ‘0’
end if; ‘0’ 5 ‘1’ ‘1’
end loop; ‘1’ 6 ‘0’ --
‘1’ 7 ‘1’ ‘0’
ODD <= p;
‘0’ 8 ‘0’ --
EVEN <= not p;
‘0’ 9 ‘1’ ‘1’
end process;
end parity9p;
architecture parity9p of parity9 is
begin
example: I =“100110101”
process (I) I(1) … I(9)
variable p : STD_LOGIC; p j I(j) p:=not p
begin ‘1’
p := I(1); ‘1’ 2 ‘0’ --
for j in 2 to 9 loop ‘1’ 3 ‘0’ --
if I(j) = '1' then p := not p; ‘1’ 4 ‘1’ ‘0’
end if; ‘0’ 5 ‘1’ ‘1’
end loop; ‘1’ 6 ‘0’ --
‘1’ 7 ‘1’ ‘0’
ODD <= p;
‘0’ 8 ‘0’ --
EVEN <= not p;
‘0’ 9 ‘1’ ‘1’
end process;
end parity9p; ODD <=‘1’, EVEN<=‘0’
 6.9 Comparators
6.9.1 Structure
1-bit comparator
（ The active-high
output is asserted
if the inputs are
different ）

4-bit comparator
6.9.2 Iterative Circuits
Cascaded by n identical modules
6.9.3 Iterative Comparator Circuit
Compare two n-bit values X and Y
6.9.4 8-bit Magnitude
Comparator

Asserted if all 8
input pairs are equal.

Asserted if
P[7-0]>Q[7-0]