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ITEC352 Lecture28
ITEC352 Lecture28
Lecture 28
Memory(5)
Review
• P2 coming on Friday
• Exam 2 next Friday
• Operating system / processes
• Logical address / physical address
• Pages / frames
• Main memory HD
Memory (5)
Demand Paging
• In other words, some pages in the process are not loaded into
the physical memory – as long as they are not needed.
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Page Table
– • The page table maps between virtual memory and physical
memory.
Memory (5)
Address translation
Contains a
present
bit
Memory (5)
Demand Paging: only bring in the pages that are needed (e.g., page 7 for program A is not needed) .
Memory (5)
Steps in Handling a Page Fault
Memory (5)
Example
Memory (5)
Performance of
paging
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Decreasing page
faults.
Memory (5)
Example
• Here is the order in which the pages are being accessed as the
process executes:
– 7, 0, 1, 2, 0, 3, 0, 4, 2, 3, 0, 3, 2, 1, 2, 0, 1, 7, 0, 1
– How many page faults occur with the:
• Optimal page replacement algorithm?
• Least Recently Used?
– Exercise in class….
• Use a separate cache (other than L1, L2) to store a part of the “page
table”.
– Called Translation look aside buffer (TLB):
• TLB is
– Hardware implementing associative memory
• Associative memory: similar to a hash table.
• Working of a TLB:
– First use page number to index into TLB,
• If page number found (TLB hit), read associated frame number
– This is faster than memory lookup since TLB is hardware implemented.
• If page number not found (TLB miss), go to main memory
Memory (5)
Paging Hardware With TLB
© Silberschatz
and Galvin
Advantage of
TLB
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Thrashing
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Putting it All Together
• An example TLB holds 8 entries for a system with 32 virtual pages and 16 page frames.
Memory (5)
Class exercise.
• Consider a memory architecture that contains a TLB, an L1 cache, an L2
cache and main memory.
• 30%: hit rate of TLB.
• 90%: hit rate of L1 cache
• 95%: hit rate of L2 cache
• 10% page fault rate.
• Also accessing
– TLB: 10 ns
– L1 cache: 15 ns
– L2 cache: 100 ns
– Memory: 100 milliseconds.
– Time to process a pagefault = 200 milliseconds
• What is the effective memory access time? (i.e., for any logical
address that the CPU requests, how long does it take on average to
read the data at that address?
Memory (5)
Summary
• Paging
• Faults
• TLB
Memory (5)