Memory

Memory
Storage units within the computer

Refers to main memory, ROM and RAM, Cache

Constructed with some basic storage units called registers

 Register
The term register can be used in a variety of specific
applications, but in all cases, it refers to a group of flip-
flops used to hold data.

There are two basic types of registers

shift and parallel.
Names are given according to the number of cells and
contains a function of the interpretation of the data stored in
it.
 Shift Registers
Capable of shifting its information either to the left or to
the right

Accept information from some input source and then

shifts the information along a chain of flip-flops, moving
it each time a positive-going clock signal occurs.

All flip-flops within the register receives a common clock

pulse
 Shift Registers
Shift Register implemented using D flip-Flops

Serial Serial
Input D Q D Q D Q D Q Out

Clock
Pulse
(CP)
 Shift Registers
Example: The bit stream 11011101 is to be stored in a 8-bit
Shift-Right register which currently contains 11011011.
Show the contents of the register after each of 6 shifts.
Input stream: 11011101

Initial 1 1 0 1 1 0 1 1
content

Shift 1
Shift 2
Shift 3
Shift 4
Shift 5
Shift 6
 Shift Registers
Example: The bit stream 11011101 is to be stored in a 8-bit
Shift-Right register which currently contains 11011011.
Show the contents of the register after each of 6 shifts.
Input stream: 1101110

Initial 1 1 0 1 1 0 1 1
content

Shift 1 1 1 1 0 1 1 0 1
Shift 2
Shift 3
Shift 4
Shift 5
Shift 6
 Shift Registers
Input stream: 110111

Initial 1 1 0 1 1 0 1 1
content

Shift 1 1 1 1 0 1 1 0 1
Shift 2 0 1 1 1 0 1 1 0
Shift 3
Shift 4
Shift 5
Shift 6
 Shift Registers
Input stream: 11011

Initial 1 1 0 1 1 0 1 1
content

Shift 1 1 1 1 0 1 1 0 1
Shift 2 0 1 1 1 0 1 1 0
Shift 3 1 0 1 1 1 0 1 1
Shift 4
Shift 5
Shift 6
 Shift Registers
Input stream: 1101

Initial 1 1 0 1 1 0 1 1
content

Shift 1 1 1 1 0 1 1 0 1
Shift 2 0 1 1 1 0 1 1 0
Shift 3 1 0 1 1 1 0 1 1
Shift 4 1 1 0 1 1 1 0 1
Shift 5
Shift 6
 Shift Registers
Input stream: 110

Initial 1 1 0 1 1 0 1 1
content

Shift 1 1 1 1 0 1 1 0 1
Shift 2 0 1 1 1 0 1 1 0
Shift 3 1 0 1 1 1 0 1 1
Shift 4 1 1 0 1 1 1 0 1
Shift 5 1 1 1 0 1 1 1 0
Shift 6
 Shift Registers
Input stream: 11

Initial 1 1 0 1 1 0 1 1
content

Shift 1 1 1 1 0 1 1 0 1
Shift 2 0 1 1 1 0 1 1 0
Shift 3 1 0 1 1 1 0 1 1
Shift 4 1 1 0 1 1 1 0 1
Shift 5 1 1 1 0 1 1 1 0
Shift 6 0 1 1 1 0 1 0 1
 Parallel Registers
So called because of the way in which input and output
values are transferred into and out of the register
respectively.

If there are a number of inputs and they are loaded

simultaneously with the CP, the loading is said to be in
parallel.

The CP thus serves as an enable signal to control the

loading of the new information into the register.
 Parallel Registers
4-bit parallel-in/parallel-out register connected to an input
and output bus.
 
INPUT
BUS
D D D D

Q Q Q Q
CP
CONTROL
SIGNALS
OE

OUTPUT
BUS
 Parallel Registers
The register has two control signals, CP (clock pulse) and OE
(output enable),
both of which are connected to all the FFs. These signals are
used to decide what specific CP will have an effect on a particular
register.
Normally, both signals are in an inactive state but will
occasionally be asserted.
The result is that when the CP is asserted, the contents of the
register is loaded from the input bus.
When OE is negated, the register is disconnected from the
output bus and when it is asserted, the contents of the registers are
put onto the output bus.
 Parallel Registers
Example: The bit stream 11011101 is to be stored in a 8-bit
Parallel register which currently contains 11011011. Show
the contents of the register after each of 6 shifts.

Input stream: 11011101

Initial 1 1 0 1 1 0 1 1
content

Shift 1 1 1 0 1 1 1 0 1
 ROM/RAM
RAM (Random Access Memory) and ROM (Read-Only
Memory)
primary memory areas within the computer. Others include

registers used in the control unit (CU) and in the arithmetic

logic unit (ALU).
Memory units consist of a set of storage registers, each of

which is identified with an address that allows the control

unit to either write to or read from it.
 RAM
sometimes referred to as the main memory.
accepts new information for storage to be available for
retrieval at a later time.
organized into words of fixed lengths (word
length/memory word)with each word having an address,
which normally starts at 0 and run consecutively.
Named based on number of words stored and number of
bits per word.
For example, a memory with 4096 locations each capable of
storing 16 bits is called a 4096-word 16-bit memory or a 4K
16-bit memory (1024 bytes = 1KB).
 RAM
Each RAM chip is made up of:
Memory Word: Group of bits that move in and out of
memory as a unit. Most computers use words that are
multiple of 8 bits (one byte).
Data Input Lines: Carries information that is to be stored
in memory.
Data Output Lines: Supplies the information coming out
of memory.
Address Selection Lines: Allows for the selection of a
word in memory from the many available.
 Memory Unit Size: Determined by the number of
memory words and the size of each memory word.
 RAM
The diagram below represents n words with a word length of m bits

word length / memory word

Address 0

Address 1

Address 2
n words

Address n -1

Bit 1 Bit 2 Bit m

Note: n is generally a power of 2 and m is generally a multiple of 8 bits (1 byte).

 RAM
An m word memory unit with n bits per word consists of mxn
binary storage cells (BC) and circuitry for selecting individual
words from the memory unit. The BC is the building block of a
memory unit. It stores one bit of information and may be
represented as below
SELECT
SELECT

R
Q OUTPUT INPUT OUTPUT
BC

INPUT S
READ/WRITE

READ/WRITE
Logic Diagram Block
Diagram
Memory Arrays
RAM
Can store n-bit binary words. An m x n array consists of m rows (words), each
row containing n cells.

Example: memory that stores 4 words each 4 bits in length i.e. a 4 x 4 array.
 ROM
• Read only Memory (ROM) is a memory
device in which permanent binary information
is stored.

2k x n
k address lines n data output
ROM
 ROM
The number of words in a ROM is determined from the
fact that k address lines are needed to specify 2k words.

Example: a 32x8 ROM

• Consists of 32 words of 8 bits each
• Has 5 input lines that form the numbers 0 through
31 (25 – 1) for the addresses.
 ROM
Operation (for the 32x8 ROM chip):
o Five inputs decoded into 32 distinct outputs each
representing one address by means of a 5x32 decoder.
o The 32 outputs of the decoder is connected to each of 8
OR gates.
o The ROM contains 256 internal connection (intersection
of 32 decoder outputs and the 8 OR gates).
o Information is stored by considering whether the
connection is close (meaning the two lines are
connected) or open (meaning the two lines are
disconnected).
 ROM
• There are two ways of viewing the specifications for
this ROM chip:
1. Each word in ROM is specified by an entry in a
truth table. For example the content of a 32 x 8
ROM may be specified with a truth table as shown
below. The complete table must include the list of
all 32 words
 ROM
ROM Truth Table (Partial)
Inputs Outputs
I4 I3 I2 I1 I0 A7 A6 A5 A4 A3 A2 A1 A0
0 0 0 0 0 1 0 1 1 0 1 1 0
0 0 0 0 1 0 0 0 1 1 1 0 1
0 0 0 1 0 1 1 0 0 0 1 0 1
0 0 0 1 1 1 0 1 1 0 0 1 0
    .                    
.

1 1 1 0 0 0 0 0 0 1 0 0 1
1 1 1 0 1 1 1 1 0 0 0 1 0
1 1 1 1 0 0 1 0 0 1 0 1 0
1 1 1 1 1 0 0 1 1 0 0 1 1
 ROM
For each word stored in ROM, a 0 specifies a no connection while
a 1 specifies a path that is obtained by a connection.
 ROM
• There are two ways of viewing the specifications for
this ROM chip:
2. Each outputs is given in relation to the
corresponding minterm values.

For example: A7 = Σm(0, 2, 3, 29)

A6 = Σm(2, 29, 30)

A7 = Σm(0, 2, 3, 29)