Professional Documents
Culture Documents
VLSI Design and ECE: Dr. B. R. Ambedkar National Institute of Technology Jalandhar Dr. Mamta Khosla
VLSI Design and ECE: Dr. B. R. Ambedkar National Institute of Technology Jalandhar Dr. Mamta Khosla
Wire-interconnect length
Temperature variations
Capacitive coupling
Material imperfections and
Differences in input capacitance on the clock inputs
Difference between arrival time of the clock
at different devices
Timing Diagram of Clock Skew
Positive Skew and Negative Skew
When both data and clock are When both data and clock are
travelling in same direction. travelling in opposite direction.
Positive Skew:
Timing Diagram of Positive Skew
Negative Skew
Timing Diagram of Negative Skew
Set Up and Hold Time
Set Up Time-
It is defined as the minimum amount
of time BEFORE the clock's active edge
by which the data must be stable for it to
be latched correctly.
Hold time-
It is defined as the minimum amount of
time after the clock's active edge during
which data must be stable
Set Up and Hold Conditions
No Clock Skew
Tcq + Tcombo = TA
Tcq - Tsetup = TR
TR : Required Time
TA : Arrival Time
With Clock Skew
TA>TR
Violation
TA<TR
Good condition for setup