Polyphase V1.05

You might also like

Download as ppt, pdf, or txt
Download as ppt, pdf, or txt
You are on page 1of 28

DSP C5000

Chapter 20
Polyphase FIR Filter
Implementation
for Communication Systems

Copyrig
Multirate Processing 1 of 2
 Multirate processing arises in many fields
of digital signal processing:
 Digital audio: sampling frequency conversion
(32 kHz, 44.1kHz, 48kHz), sharp cut-off of FIR
filter, …
 Signal processing for digital communications:
symbol rate processing, bit rate processing,
sample rate processing, …
 Speech processing: 3G speech codec (Adaptive
Multi Rate), fractionnal pitch estimation, ...
 …

SIEE, Slide 2 Copyrig


Multirate Processing 2 of 2
 Involves two actions on the digital signal:
 Downsampling: resampling downwards the
digital signal in the digital domain.

Fe Fe/M Retain one sample over M and discard


M
the M-1 others, every M samples.

 Upsampling: resampling upwards the digital


signal in the digital domain.

Fe LFe Insert L-1 zeros between each sample


L

SIEE, Slide 3 Copyrig


Downsampling 1 of 2
 x( n) if n  mM ,
x(n) M y(m) y( m )  
0 else.


1 1 M 1 k
y( m )  x ( mM )   x( n) ( n  mM ) 
j 2 n

m   M
x( n) 
M
 x( n)e
k 1
M

Folding term
SIEE, Slide 4 Copyrig
Downsampling 2 of 2
 Anti-aliasing Filter
fc : (Fe/M)/2
x(n) H(z) M y(m)

Fe Fe/M

 Noble identity for decimation

H(zM) M M H(z)

SIEE, Slide 5 Copyrig


Upsampling 1 of 2
 x ( m ) if n  mL ,
x(m) L y(n) y( n)  
0 else.

   
 
Y (z)   y( n) z
n  
n
  x( m ) z
m  
L m
 X zL

SIEE, Slide 6 Copyrig


Upsampling 2 of 2
 Interpolating Filter

fC : (Fe/L)/2
x(m) L H(z) y(n)

Fe LFe

 Noble identity for upsampling


L H(zL) H(z) L

SIEE, Slide 7 Copyrig


Polyphase Implementation of FIR Filters
Decimation Case 1 of 4
H(z) M E(zM) M

mM 1
H  z   h( n ) z n

n0

Let n=lM+k

 
M 1 N / M 1
H  z   z Ek z
k M
with Ek  z    h lM  k  z l

k 0 l 0

SIEE, Slide 8 Copyrig


Polyphase Implementation of FIR Filters
Decimation Case 2 of 4
Processing load (MAC/s)
H(z) M
N

E0(zM)
z-1
E1(zM) MTe Time
z-1
• M-1 filter evaluation over M

EM-1(zM) M are discarded.


• N filter length

Fe Fe/M
SIEE, Slide 9 Copyrig
Polyphase Implementation of FIR Filters
Decimation Case 3 of 4
 Using noble identity

Processing load (MAC/s)


M E0(z)
z-1 N
M E1(z)

z-1
M EM-1(z)
MTe Time

Fe Fe/M
• No more useless computations, but one sampling period over M, CPU is
burdned with N MAC/s.

SIEE, Slide 10 Copyrig


Polyphase Implementation of FIR Filters
Decimation Case 4 of 4
 Equivalent commutator model

Processing load (MAC/s)


E0(z)

E1(z)

N/M

EM-1(z)
MTe Time

Fe Fe/M
• Commutator runs at Fe,. At each input sample only one component is computed and accu-
mulated with the result of the previous one. The result is output when the last component
is reached and accumulator is reset. This spreads the processing load over MTe.
SIEE, Slide 11 Copyrig
Polyphase Implementation of FIR Filters
Interpolation Case 1 of 5
L H(z) L R(zL)

lL 1
H  z    h( n) z  n
n0

Let n=mL+L-1-k

 
L 1 N / L 1
H  z   z  ( L 1  k )
Rk z L
with Rk  z    h mL  L  1  k  z m

k 0 m 0

SIEE, Slide 12 Copyrig


Polyphase Implementation of FIR Filters
Interpolation Case 2 of 5
Processing load (MAC/s)
L H(z)
N

L R0(zL)
z-1

R1(zL) Te/L Time

z-1 • L-1 multiplications by 0 over L


For each filter evaluation.
RM-1(zL)
• N filter length.

Fe LFe
SIEE, Slide 13 Copyrig
Polyphase Implementation of FIR Filters
Interpolation Case 3 of 5
 Using noble identity

R0(z) L • At each output sampling instant,


z -1
only one component is non zero

R1(z) L

z-1
RM-1(z) L

Fe LFe

SIEE, Slide 14 Copyrig


Polyphase Implementation of FIR Filters
Interpolation Case 4 of 5
 Equivalent commutator model

R0(z) Processing load (MAC/s)

R1(z)

N/L

RM-1(z)
Te/L Time
Fe LFe
• For each output sampling instant one polyphase component is computed.
When we reach again the first component (M-1) a new input sample is inputed
in the delay line of each polyphase component.
SIEE, Slide 15 Copyrig
Polyphase Implementation of FIR Filters
Interpolation Case 5 of 5
 Linear Periodically Varying Time system

z-1 z-1

hL-1 h2L-1 h3L-1 z-1 z-1

z-1 z-1

h1 hL+1 h2L+1 h0 hL h2L


h1 hL+1 h2L+1

z-1 z-1 hL-1 h2L-1 h3L-1

h0 hL h2L

SIEE, Slide 16 Copyrig


Case Study

 Shaping filters for a QPSK modem :


 Emitter: interpolation case.
 Receiver: decimation case

 Efficient Algorithm Implementation :


 Good ordering of computations,
 Efficient memory organization and management.

SIEE, Slide 17 Copyrig


Emitter 1 of 4
s(t)=1/2[cos(2fot).cos((Ak,Bk))-sin(2fot).sin((Ak,Bk))]
s(t)=1/2[cos(2fot).cos((Ak,Bk))-sin(2fot).sin((Ak,Bk))]

QPSK modulator
Ak Cos() RCF DAC
: Phase

bits computation
Bk
Sin() RCF DAC

Fb Fs Fe
Bit Symbol Sample
frequency frequency frequency

SIEE, Slide 18 Copyrig


Emitter 2 of 4
 Let Fe=16Fs (16 sample / symbol)
 Define a raised cosine filter with:
 6 symbols length.
 Roll_off : 0.5
 Matlab command
 h=RCOSFIR(0.5,3,16,1);
Equivalent system

16 H(z)

• In red: ideal interpolating filter


• In blue: actual RC filter

SIEE, Slide 19 Copyrig


Emitter 3 of 4
 The 16 Polyphase filters are defined by :
Filter length is 97, impulse response is padded with 0 to reach 112=7*16

N / L 1
Rk  z    h mL  L  1  k  z m With N=112 and L=16

m 0

r0  m    h 15 , h 31 , h 47  , h 63 , h 79 , h 95 , h 111  


r1  m    h 14 , h 30 , h 46 , h 62 , h 78 , h 94 , h 110  
 
r15  m    h 0 , h 16 , h 32 , h 48 , h 64 , h 80 , h 96 

SIEE, Slide 20 Copyrig


Coefficients
Emitter 4 of 4
h(0)
h(16)
h(32)
h(48)
h(64)
h(80)
h(96)
Symbols Shuffle coefficients
h(1)
h(17) x(0)
1st sample h(33) x(1) R=flipud(reshape(h,8,12));
2nd sample h(49) x(2)
h(65) x(3) R=round(R*2^15);
h(81) x(4)
h(97) x(5) fid=fopen('coef.inc','wt');
15 sample
th x(6)
for p=1:8
fprintf(fid,'\t.word\t%d\n,R(p,:))
end

h(15) fclose(fid);
h(31)
h(47)
h(63)
h(79)
h(95) When coefficient pointer reaches this address a new
h(111)
symbol will be input at the next output sample period
SIEE, Slide 21 Copyrig
Emitter (C callable)
.sect "coefs2"
Ncomp .set 16 ;number of polyphase component
coefs2 .include "coefpoly2.inc"
coefsfin:
coefsize .set coefsfin-coefs2
Lfil .set coefsize/Ncomp ;polyphase component length
filbufQ .usect "filtre2",Lfil ;data buffer

.text
_firinit:
ST #coefs2,*(adbufQ) ;pointer to current coefs pointer
STM #filbufQ,AR2 ;zeroed initial buffer condition
RPT #Lfil-1
STL A,*AR2+
RET

SIEE, Slide 22 Copyrig


_firTxQ:… ;context save
LD #var,DP
STM #coefsize,BK
MVDM adbufQ,AR2 ;current coefs pointer
STM #1,AR0
STM #filbufQ,AR3 ;symbol buffer
STL A,*AR3 ;new sample (guess hold during 16 samples)
RPTZ A,#Lfil-1 ;compute one polyphase component
MAC *AR2+0%,*AR3+,A
MVMD AR2,adbufQ ;save new current coefs pointer
SFTA A,-16
SFTA A,-1 ;output of RCF can be greater than 1 !
CMPM @adbufQ,#coefs2 ;test if delay symbols is needed
BC endTxQ,NTC ;jump if not necessary
MAR *+AR3(-2)
RPT #Lfil-2
DELAY *AR3-
endTxQ:
… ;context restore
RET
SIEE, Slide 23 Copyrig
Symbol vs Sample Output
Symbol output Sample output

Fe: 16 khz f= Fs/8=125 Hz


Fs: 1 khz
constant for each symbol

SIEE, Slide 24 Copyrig


Receiver 1 of 2

Bit Symbol
processing processing

ADC RCF

ADC RCF

Fe Fb Fs

SIEE, Slide 25 Copyrig


Receiver 2 of 2
 Receiver structure is quite similar, except
that:
 Each polyphase component has its own delay tap
 Each polyphase output has to be accumulated for M
polyphase computations and accumulator is outputed
every M input sample and reset.

E0(z)

E1(z)

EM-1(z)

SIEE, Slide 26 Copyrig


Follow on Activities
 Laboratory 10 for the TMS320C5416 DSK
 Illustrates the effects of decimation and anti-
aliasing filters.
 Laboratory 11 for the TMS320C5416 DSK
 Illustrates the effects of interpolation and anti-
imaging filters.
 Application 9 for the TMS320C5416 DSK
 Uses interpolation and decimation to produce
sharper cut-offs FIRs than would be obtained
otherwise.

SIEE, Slide 27 Copyrig


Reference
 Digital Signal Processing a Practical
Approach by Emmanuel C. Ifeachor
and Barrie W. Jervis. Chapter 9. Multirate
digital signal processing.

SIEE, Slide 28 Copyrig

You might also like