MEU 07401

Digital Electronics

Lecture 08
Sequential Logic Circuits
 Definition  SR-FF, JK-FF, D-FF
 Flip-flops  Synchronous and asynchronous inputs
 NAND latch  master/slave FF
 NOR latch  flip-flop applications
 clock signal and clocked flip-
flops

1
 Introduction
Sequential logic circuit - one whose outputs depend
not only on the present inputs, but also on the past
history

Examples include: –
Traffic light controller Electronic combination lock

2
Combinational vs. Sequential Circuits

3
 Sequential Circuits

A sequential circuit consists of a feedback

path, and employs some memory elements.

° Combinational
outputs ° Memory outputs

° Combinational ° Memory elements

logic

° External inputs

Sequential circuit = Combinational logic + Memory Elements

4
 Types of Sequential Circuits
• Synchronous  State changes occur in
synchronisation to a clock signal
• Input changes occur between clock pulses
• State changes occur at the clock pulses
• Asynchronous  State changes occur as changes in
inputs occur. It is event driven
• What is a clock? A square wave of fixed frequency.
Often, transitions will occur on one of the edges of
clock pulses, i.e. the rising edge or the falling edge

5
Types of Sequential Circuits

6
 Triggering
 Synchronous Sequential circuits are dependent on
clock pulses applied to their inputs (so that inputs
don’t change randomly)
 The result of flip-flop responding to a clock input is
called clock pulse triggering, of which there are
four types. Each type responds to a clock pulse in
one of four ways :-
1. High level triggering

2. Low level triggering

3. Positive edge triggering
4. Negative edge triggering
 Memory Elements
Memory element: a device which can remember
value indefinitely, or change value on command
from its inputs
° Memory ° Q
° comman element ° stored
d value

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 Basic Memory Elements

Latch
 Clock input is level sensitive
 Output changes while clock is active


Flip Flop
 Clock input is edge sensitive
 Output changes on clock transition

The Clock 

13
 Memory Elements
 Pulse-triggered
latches
ON = 1, OFF = 0
 Edge-triggered
flip-flops
positive edge-triggered (ON = from 0 to 1;
OFF = other time)

negative edge-triggered (ON = from 1 to 0;

OFF = other time)

14
 Latch

Latch are the devices which responds to the

change of input logic levels as they occur.

Q
Complementory
Input output
s Latch Q is the primary
Q output
Q is its complemetory

It is said to be in SET state if output Q is high

It is said to be in RESET state if output Q is low
 Flip-Flops
– Flip-flops
are the fundamental element of
sequential circuits
– Gates are the fundamental element for
combinational circuits
– Flip-flops are essentially 1-bit storage devices
– Outputs can be set to store either 0 or 1
depending on the inputs
– Even when the inputs are de-asserted, the
outputs retain their prescribed values
– Flip-flops
have (normally) 2 complimentary
outputs Q and Q'

16
 Set-Reset (S-R) Latch

• The SR latch is a circuit with two cross-

coupled NOR gates or two cross-coupled
NAND gates, and two inputs labeled S for
set and R for reset

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 S-R Latch with NORs

R (reset) Q S R Q Q’
1 10 0 Undefined
1 0 1 0 Set
Q 0 1 0 1 Reset
S (set) 0 0 0 1 Stable
1 0 No changes
° S-R latch is made from cross-coupled NORs
° If Q = 1, set state
° If Q = 0, reset state
° Usually S=0 and R=0-No changes in output
° S=1 and R=1 generates unpredictable results
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 S-R Latch
 Complementary outputs: Q and Q‘

 When Q is HIGH, the latch is in SET state

 When Q is LOW, the latch is in RESET state

 For NOR gate latch,

 R=HIGH (and S=LOW) a RESET state
 S=HIGH (and R=LOW) a SET state
 both inputs LOW a no change
 both inputs HIGH a Q and Q' both LOW (invalid)!

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 S-R Latch with NANDs

S S R Q Q’
Q
0 0 1 1 Disallowed
0 1 1 0 Set
1 0 0 1 Reset
Q’
R 1 1 0 1
1 0 Store

° Latch made from cross-coupled NANDs

° Usually S=1 and R=1
° S=0 and R=0 generates unpredictable results

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 S-R Latch
 For NAND gate latch,
 R=LOW (and S=HIGH) a RESET state
 S=LOW (and R=HIGH) a SET state
 both inputs HIGH a no change

 both inputs LOW a Q and Q' both HIGH (invalid)!

 Drawback of S-R latch: invalid condition exists

and must be avoided

21
 S-R Latch
NOR Gate S-R latch
° °1 0
° °1°0 0
R S R QQ '
Q ° °1°1°0°0 0
1 0 1 0 in
itia l
0 0 1 0 (afe
rS = 1 ,R =
0)
0 1 0 1
° °1 0
° °0°0 1S Q' ° °0°0°1°1 0
0 0 0 1 (a
fterS = 0 ,R =1)
1 1 0 0 inva lid!
A NAND Gate S-R latch

S S R Q Q'
Q 1 0 0 1 initial
1 1 0 1 (afer S=1, R=0)
0 1 1 0
Q’ 1 1 1 0 (after S=0, R=1)
R
0 0 1 1 invalid!

S-R Latch 22
S-R Latches

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 S-R Latch with Control Input

° Occasionally, desirable to avoid latch changes

° C = 0 disables all latch state changes
° Control signal enables data change when C = 1
° Right side of circuit same as ordinary S-R latch

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Timing Diagram for S-R Latch With Control Input

Q’
Set Reset

25
S-R Flipflop Characteristic Table

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 Excitation table
SR flip-flop:-
Clk S R Qn Qn
0 0 No change
0 1 0 1
1 0 1 0
1 1 invalid
Excitation table:-

Present state of Next state of Q Sn Input Rn input

Q o/p o/p
0 0
0 1
1 0
1 1
0 ×
1 0
0 1
× 0
 D Latch
° Q0 indicates the previous state (the previously
stored value)
X
D S
Q
C

Q’

Y R
X Y C Q Q’
D C Q Q’
0 0 1 Q0 Q0’ Store
0 1 0 1
1 1 1 0 0 1 1 0 1 Reset
X 0 Q0 Q0’ 1 0 1 1 0 Set
1 1 1 1 1 Disallowed
X X 0 Q0 Q0’ Store
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 D Latch
X
D S
Q
C

Q’

Y R
D C Q Q’
0 1 0 1
1 1 1 0
X 0 Q0 Q0’
° Input value D is passed to output Q when C is high
° Input value D is ignored when C is low

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 D-Type Flip-Flop
• D is stored when the clock goes from 0 to 1
• Small triangle indicates edge-triggered.

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 Symbols for Latches

° SR latch is based on NOR gates

° S’R’ latch based on NAND gates
° D latch can be based on either.
° D latch sometimes called transparent latch

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 D Flip-Flop
° Stores a value on the positive edge of C
° Input changes at other times have no effect on output

Positive edge triggered

D C Q Q’
D Q
0 0 1
C Q’ 1 1 0
X 0 Q0 Q0’

D gets latched to Q on the rising edge of the clock.

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Positive and Negative Edge D Flip-Flop
° D flipflops can be triggered on positive or negative
edge
° Bubble before Clock (C) input indicates negative edge
trigger

Lo-Hi edge Hi-Lo edge

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Characteristics Table of D-Flip flop

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Excitation Table of D- Flip flop
JK Flip flop

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 JK-Type Flip-Flop
• 4 possible operations
– J=0, K=0: no change
– J=0, K=1: reset condition
– J=1, K=0: set condition
– J=1, K=1: toggle condition

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 Clocked J-K Flip Flop
° Two data inputs, J and K
° J -> set, K -> reset, if J=K=1 then toggle output

Characteristic Table

38
Characteristics Table of JK-Flip flop

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 Excitation Table of JK- Flip flop
JK flip-flop:-
Clk J k Qn Qn
0 0 No change
0 1 0 1
1 0 1 0
1 1 Qn Qn

Excitation table:-
Present state of Next state of Q
Q o/p o/p
0 0
0 1
1 0
1 1
Jn Input Kn input
0 ×
1 ×
× 1
× 0
 T Flip-Flop

° Created from JK Flip flop

° T=0 - keep current
° T=1 -invert current

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Characteristic Table for T-Flip flop
T flip-flop:-
Clk T Q
0 No change
1 toggle

Excitation table:-
Present state of Next state of Q Tn Input
Q o/p o/p
0 0 0
0 1 1
1 0 1
1 1 0
Summary
TRUTH TABLE