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Inverter: Basic Requirement For Producing A Complete Range of Logic Circuits
Inverter: Basic Requirement For Producing A Complete Range of Logic Circuits
Inverter: Basic Requirement For Producing A Complete Range of Logic Circuits
Design
1 0 Vo
0 1
Vss
Vdd
Basic Inverter: Transistor with source
connected to ground and a load resistor
Pull-Up connected from the drain to the positive
R Supply rail
Vo Output is taken from the drain and control
input connected between gate and ground
Non-zero output S
Vss
Vi
EE213 VLSI Design Stephen Daniels 2003
Ids VLSI
Design
Vgs=0.2VDD
Ids
Vgs=0
Vgs=-0.2 VDD
Vgs=-0.4 VDD
Vgs=-0.6VDD
VDD –Vds
Vds
Vin
Vgs=VDD
VDD
Ids
Vgs=0.8VDD
Vgs=0.6 VDD
Vgs=0.4 VDD
Vgs=0.2VDD
Vds
Vo
VDD VDD
VDD
Increasing
Zpu/Zpd
Vo
VDD
Vinv
Convention Z = L/W
This gives Zpu / Zpd = 4:1 for an nmos inverter directly driven by another inverter
A B C
Vin1 Vout2
It is often the case that two inverters are connected via a series of switches (Pass Transistors)
We are concerned that connection of transistors in series will degrade the logic levels into
Inverter 2. The driven inverter can be designed to deal with this. (Zpu/Zpd >= 8/1)
Vdd
P on N on
Vin Vo N off P off
Both On
Vin
Vss Vdd
Vss Logic 1
Logic 0
1: Logic 0 : p on ; n off
P on N on 5: Logic 1: p off ; n on
N off P off
Both On 2: Vin > Vtn.
Vdsn large – n in saturation
Vdsp small – p in resistive
Small current from Vdd to Vss
1 2 3 4 5
pW p W
n 2 p n n
Vin Vtn Vin VDD Vtp 2 Lp Ln
2 2
p
n
2
Vin Vtn
2
Vin VDD Vtp
Mobilities are unequal : µn = 2.5 µp
n
Vin Vtn Vin VDD Vtp
p Z = L/W
n n
Vin 1 Vtn VDD Vtp
p p Zpu/Zpd = 2.5:1 for a symmetrical CMOS inverter