Research Interests are:

Signal Integrity in VLSI

(Very Large Scale Integrated
Circuits).
• Testing of VLSI Circuits: Non-contact Testing
• Interconnect crosstalk noise and delay analysis
and modeling for DSM Technology
• Radiation Effect Modeling of Integrated Circuits
• Radiation Tolerant Circuit Design
• Low-Power Design
on chip wires (interconnects) 2
couplings among multiple layers of interconnect
Due to the radioactive decay of the packaging material
or due to the terrestrial radiation, high-energy alpha and
neutron particles can originate and can create current
pulses on circuit nodes.

4
 LOGIC DATA REVERSAL ON STORAGE
ELEMENT OR SOFT ERROR GENERATION
VLSI Stands for Very Large Scale Integration

VLSI Integration refers for the process of placing 100’s

of thousands (OR MORE) of transistors on a single chip.

The fundamental measure of a wafer fabrication is the

minimum feature size, it is capable of producing on a
wafer.

Smaller is better, because this allows more transistors

and other components to be packed onto a chip of a
given size.
Minimum feature size usually refers to
the channel length of the transistor, and this also
refers to the minimum poly line width.

Feature size gives its name to the technology.

i.e. 1 µ technology etc.

The IC industry started with 10 micron technology
in early 1970’s

Through 1980's the technologies were mostly in

5 m to 1m (or the feature size). Advances in
photolithography led to line widths below 1 m by
scaling (submicron technology).
technology

As scaling continued it became 0.35 m during

1990's. Beyond this point it is called as Deep Sub
Micron Technology (DSM).
0.35 um was thought to be a barrier to the
technology since this is the wavelength of the
light used in photolithography.

Although this barrier has been overcome, we

started to observe short-channel effects with
0.35 micron technology (Deep submicron
technology):
DSM Technology led to following problems :

• Due to short channel effects, the leakage current

in devices has increased

• The wires connecting transistors started to

introduce additional RC delays in the circuit due
to increased resistance.
• Increase in resistance in power distribution system
caused voltage drops in the power grid which is
called IR drops. This caused less voltage to be
delivered to logic gates decreasing noise immunity.
•Clock distribution has been a problem
clock may arrive at different arrival times to
storage elements causing a “clock skew”

The driver is located in the

corner, while target flip flops are
scattered around the chip
The arrival times of the clock to
each of the FF's will slightly
differ, some will receive clock
late, and some will receive early
relative to each other.

(due to varying wire length)

• Coupling effect between lines caused noise
injection and delay variations. Noise injections
after some point caused logic errors.
•The reliability of aluminum metal lines began to
degrade due to metal migration (electromigration).
This resulted from high current levels.
For devices, hot carrier effects are pronounced.

What are hot carriers?

The term 'hot carriers' refers to either holes or
electrons that have gained very high kinetic
energy after being accelerated by a strong electric
field within a semiconductor, i.e. MOS device.

Due to shrinking sizes of transistors, the electrical

fields can be so high to cause hot carrier effects.
Because of their high kinetic energy, hot carriers
can get injected and trapped in areas of the device
where they shouldn't be and they can cause the
device to degrade or become unstable.

They can cause shifts in threshold voltage (Vth) and

change in trans-conductance (gm).

They can even cause gate currents which should

not exist in a MOSFET.
DSM issues became more important as scaling continued
and the feature size went down to 0.13 micron.

In 2004, 90 nm silicon first appeared for microprocessors

with Intel and IBM.

45 nanometer (45 nm) tech. has now become commercially

viable as of November 2007.

Current commercial process is 22nm!

SCALING TRENDS:

Moore Law originally stated that the number of

transistors per square inch on integrated circuits
doubles every year.

The reality now has been transistors doubling every

2 years.
 (Semiconductor Industry Association)

The minimum feature size decreases by 30% every 3 years.

This has been true for almost 30 years.
What is the ITRS?
The International Technology Roadmap for Semiconductors
(ITRS) evaluates semiconductor technology requirements.

The ITRS identifies the technological challenges and needs

facing the semiconductor industry over the next 15 years.
It is sponsored by the European Semiconductor Industry
Association (ESIA), the Japan Electronics and Information
Technology Industries Association (JEITA),
the Korean Semiconductor Industry Association (KSIA),
the Semiconductor Industry Association (SIA), and
Taiwan Semiconductor Industry Association (TSIA).
ITRS Reports can be downloaded from
http://public.itrs.net/Reports.htm
Trends of VLSI chip

o More transistors
 

o Faster speed
 

o Higher power consumption

 

o Poor testability
 

o Signal Integrity problems

(Delays, Glitch induced Logic

Errors, Radiation Effects on ICs)
READING ASSIGNMENT

Please go over remaining slides!!

We implement logic functions using either
sum-of-products or products-of-sums

F=AC +BC+AD+BD
represents sum-of-products

F=(A+B)(C+D)
represents products-of-sums representation of
same function
Demorgan’s Rule:

(a+b)’= a’ . b’
(a.b)’ = a’ + b’

Which gives two possible representation

for NAND and NOR gates.
Demorgan’s Rule
Other combinational gates such as
XOR and XNOR functions are also useful
XOR gate
F=A + B = AB’+A’B

XNOR gate
F=A . B = AB +A’B’
Positive edge triggered D type flip flop
For a logic gate

forbidden
region
Each logic gate has

VIH, VIL, VOH and VOL

which determine the noise margins

5V
5V

4V
3V
2V
1V
 (propagation delay)

(rise time or fall time)

always refers to the transition on the output