DWARAKA DOSS GOVERDHAN DOSS

VAISHNAV COLLEGE
CHENNAI -106

SUBJECT: FUNDAMENTALS OF DIGITIAL ELECTRONICS

Presented By,
Panneer Selvam E
Assistant Professor
XOR GATE
A B Output
0 0 0
0 1 1
1 0 1
1 1 0

Boolean Expression = AB’+A’B

It’s a Hybrid gate, the boolean expression of this gate is given by combining
multiplication, Addition of inputs.
Arithmetic Logic Units
Half Adder

 Basic module used in binary arithmetic elements is the half-

adder.
 The function of half-adder is to add two binary digits,
producing sum and carry according to the binary addition
A B S C
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

 S = AB’+A’B // (A xor B)
 C = AB
Full Adder

 There are three inputs to the full binary adder and

produce two outputs such as sum and carry
A B C S C0
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

S = A’B’C +A’BC’+AB’C’+ABC
C = A’BC+AB’C+ABC’+ABC = AB+BC+AC
S= A’B’C +A’BC’+AB’C’+ABC
C(A’B’+AB) + C’(A’B+AB’)
C(A xnor B) + C’(A xor B)
C(A xor B)’ + C’(A xor B)
C xor ( A xor B)

C = AB+BC+AC (B’+B)
= AB+BC+AB’C+ABC
=AB(1+C)+BC+AB’C
=AB+BC(A+A’)+AB’C
=AB+ABC+A’BC+AB’C
=AB+C(A’B+AB’)
=AB+C(A XOR B)
Half Subtractor
 The function of half-subtractor is to sub two binary digits,
producing difference and borrow according to the binary addition

A B D Borrow
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
 D=A’B+AB’ // A XOR B
 Borrow = A’B
Full Subtractor
 There are three inputs to the full subtractor and produce two outputs such as
difference and borrow
A B C Diff Borro
w
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
Diff= A’B’C+A’BC’+AB’C’+ABC
Borrow=A’B’C+A’BC’+A’BC+ABC
Diff= A’B’C+A’BC’+AB’C’+ABC
C(A’B’+AB) + C’(A’B+AB’)
C(A XNOR B) + C’(A XOR B)
C(A XOR B)’ + C’(A XOR B)
C XOR (A XOR B)

Borrow = A’B’C+A’BC’+A’BC+ABC
=001+010+011+111
=M(1,2,3,7)
using k-map = A’C+A’B+BC
Borrow = A’C+A’B+BC
= A’C+A’B+BC(A+A’)
=A’C+A’B+ABC+A’BC
=A’C+A’B(1+C)+ABC
=A’C+A’B+ABC
=A’C(B+B’)+A’B+ABC
=A’BC+A’B’C+A’B+ABC
= A’B(C+1)+C(A’B’+AB)
=A’B+C(A XNOR B)
=A’B+C(A XOR B)’
METHOD 2 (using law)
B = A’B’C+A’BC’+A’BC+ABC
= C(A’B’+AB)+A’B(C’+C)
=C(A xnor B) +A’B
=C(A xor B)’+A’B

FULL ADDER
C= A’BC+AB’C+ABC’+ABC
= C(A’B+AB’)+AB(C’+C)
=C(A XOR B)+AB
Multiplexer (MUX)

 Multiplexer is a combinational circuit used to select single

input from several inputs with the help of selection line
 It has 2n inputs, ‘n’ selection line and single output.
Enable input is used to enable or disable multiplexer
 For example: 2:1multiplexer has 2 inputs and , one output
and one select line (21 = 2)
 4:1 multiplexer has 4 inputs and 2 select line and one output
(22=4)
 Types of multiplexer are 2:1, 4:1,8:1,16:1 and so on
 Multiplexer are used in telephone network, data routing,
radio..etc
2:1 MUX
 2:1 MUX consists of two input lines (D0,D1) , one select line (S)
and one output Y
 Enable (E) control line enable or disable the multiplexer

S0 Y
0 D0
1 D1

 when S0=0 input D0 is selected and Y=D0

 when S0=1 input D1 is selected and Y=D1
 From the table Boolean expression can be given as:
Y = S0’D0+S0D1
4:1 MUX
 4:1 multiplexer consists of four input lines D0 to D3,
two select line S0 & S1 and single output line Y.
S1 S0 Y
0 0 D0
0 1 D1
1 0 D2
1 1 D3

 From the table boolean expression can be given as:

Y = S1’S0’D0+S1’S0D1+S1S0’D2+S1S0D3
Y = S1’S0’D0+S1’S0D1+S1S0’D2+S1S0D3
8:1 MUX
 8:1MUX consists of 8 input lines D0 to D7, 3
selection line S0,S1,S3 and one output line Y.
Depending on the selection line multiplexer
produce the output S2 S1 S0 Y
0 0 0 D0
0 0 1 D1
0 1 0 D2
0 1 1 D3
1 0 0 D4
1 0 1 D5
1 1 0 D6
1 1 1 D7
 From the table boolean expression can be given as:
Y=S2’S1’S0’D0+S2’S1’S0D1+S2’S1S0’D2+S2’S1S0D3+S2S1’S0’D4+S2S1’S0D5+S2S1S0’D6+S2S1S0D7

We can implement 8:1 multiplexer using lower order

multiplexers as follows:
 The data inputs of upper 4x1 Multiplexer are I 7 to I4 and the data inputs
of lower 4x1 Multiplexer are I3 to I0. Therefore, each 4x1 Multiplexer
produces an output based on the values of selection lines, s 1 & s0.
 The outputs of 4x1 Multiplexers are applied as inputs of 2x1
Multiplexer.  The other selection line, s2 is applied to 2x1 Multiplexer.
 If s2 is zero, then the output of 2x1 Multiplexer will be one of the 4 inputs
I3 to I0 based on the values of selection lines s1 & s0.
 If s2 is one, then the output of 2x1 Multiplexer will be one of the 4 inputs I 7 to
I4 based on the values of selection lines s1 & s0.
 Therefore, the overall combination of two 4x1 Multiplexers and one
2x1 Multiplexer performs as one 8x1 Multiplexer.
8:1 MUX Using Basic Gates
 Can you Solve?
1. 16:1 MUX has how many input lines, selection
lines and output line?
2. How many 8:1 multiplexer and 2:1 multiplexer
are need to implement 16:1 multiplexer
Demultiplexer (DEMUX)
 It performs reverse operation of Multiplexer. It has
single input, ‘n’ selection lines and 2n outputs.
 The input will be connected to one of these outputs
based on the values of selection lines.
 For example: 1:2 multiplexer has 1 inputs and , two
output and one select line (21 = 2)
 1:4 multiplexer has 1 input and 2 select line and four
output (22=4)
 Types of multiplexer are 1:2, 1:4,1:8,1:16 and so on
1:4 DEMUX

S1 S0 Y3 Y2 Y1 Y0
0 0 0 0 0 1
0 1 0 0 1 0
1 0 0 1 0 0
1 1 1 0 0 0
 From the table Boolean expression can be given as:
Y3=S1S0I Y2=S1S0’I Y1=S1’S0I Y0=S1’S0’I
 When AB = 01, the upper second AND gate (Y1) is
enabled while other AND gates are disabled.
Therefore, only data bit D is transmitted to the
output, giving Y1 = Data.
 If D is low, Y1 is low. IF D is high,Y1 is high.

Applications:
Communication system
ALU (to store result in multiple register)
Encoder (Octal to Binary)

 An octal to binary encoder consists of eight input

lines and three output lines. Each input line
corresponds to each octal digit and three outputs
generate corresponding binary code.
 In encoders only one input is active or has a value 1
at any given time 
 From the above table,
Y0 = D1+D3+D5+D7 ; Y1 = D2+D3+D6+D7 ;
Y2 = D4+D5+D6+D7
  D0 does not exist in any of the expressions so it is considered as don’t
care. 

Implementation using OR gate

Application : Encoders are very common electronic circuits used in all
digital systems. used to translate the decimal values to the binary in order to
perform the binary functions such as addition, subtraction, etc.
Keyboard (ASCII to Binary)
Decoder (3 to 8 decoder)

 A digital decoder converts a set of digital signals into

corresponding decimal code. A decoder is also a most
commonly used circuit in prior to the use of encoder.
 The encoded data is decoded for user interface in most
of the output devices like monitors, calculator displays,
printers, etc.
 In a 3-to-8 decoder, three inputs are decoded into eight
outputs. It has three inputs as A, B, and C and eight
output from Y0 through Y7.
  Based on the combinations of the three inputs, only
one of the eight outputs is selected.
From the table:
Y0 = A’B’C’ ; Y1=A’B’C ; Y2 =A’BC’ ; Y3 = A’BC ; Y4 = AB’C’ ; Y5 = AB’C ;
Y6 = ABC’ ; Y7 = ABC
Application :
Binary to decimal , calculator …
THANK YOU