Processor: Datapath and Control

Computer Organization & Design, Hennesy & Patterson Chapter 5 (3rd) or 4 (4th)

Augusto Salazar
Departamento de Ingeniería de Sistemas
Universidad del Norte
augustosalazar@uninorte.edu.co

Originalmente por Profesor Miguel Jimeno

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 Datapath and Control

Datapath
– Set of functional units that are in charge of
making the operations

Control
– Units on charge of controlling the flow of
signals and the functional units of the
datapath

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 MIPS Implementation
A subset of MIPS is going to be implemented

The memory reference instructions load word (lw) and store word (sw)

The R-Type instructions add, sub, and, or

The branch (beq), and jump (j) instructions

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 MIPS´s High Level View

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 MIPS Implementation
The first two steps for any instruction are the same

1-- Send the PC (program counter) to the instruction memory and fetch that
instruction

2-- Read one or more registers depending of the instruction type and using
the fields from the instruction

The third step has some similarities between instructions

3– Execution

Load and Store use the ALU to calculate the memory address (register +
offset)
Register type instructions use the ALU to make the operation
Branch uses the ALU to test the equality of the the values contained on the
registers

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 MIPS implementation

The final step differs depending of the instruction

type:
• The memory reference instrunctions needs to
access memory or a register
• The register type instrunctions need to store
the result on the register file
• The branch and jump may need need to
update the PC

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 MIPS´s High Level View

Two key aspects are missing:

Multiplexers
The data arriving to the functional units may come from different
sources

Control lines for reading/writing

– Memory has to be written on a store and read on a load.
– The register file has to be written on load or in an R-Type
instruction

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 MIPS´s High Level View
Including multiplexers and control lines

This is known as a Datapath for Single-Cycle, in which there is a long

cycle for each instruction
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 Conventions
CarryIn
Adder A
32 Logic elements

Adder
Sum
32
B Carry – Elements that
32
operate using the
input values
Selec
t – The output
A
32
MUX
depends
MUX Y
32 exclusively of the
B
32 inputs
O
– Same inputs will
P
always translate
A
32 into the same
ALU

ALU Result outputs

32
B
32
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 Conventions

State Elements
• An element has state if it has internal
storage
• Requires at least two inputs and one
output
We work with two at least two state
elements
• Registers
• Register File
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 Storage Element: Register (Basic
Building Block)

Register
– Similar to the D Flip Flop except
Write Enable
• N-bit input and output
• Write Enable input Data In Data Out
– Write Enable: N N
• negated (0): Data Out will not
change Clk
• asserted (1): Data Out will
become Data In

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 Building a datapath

The common Fetch operations

– Fetch the Instruction: mem[PC]
– Update the program counter:
• Sequential Code: PC <- PC + 4
• Branch and Jump: PC <- “something else”

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Logisim implementation
We will start our Logisim implementation, it will cover:

Instruction fetch
• PC
• Instruction memory
• Adder

Instruction decoder: it must be implemented on a

separated circuit.

The project should have a reset button connected to

all components except the instruction memory.
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Logisim implementation
The implementation must cover the following
instructions:

Tipo R: add, sub, and, or

Addi

Load, Store

Branch , Jump

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