Switches for DACs

&
High Speed Sample and Hold Circuit
 Introduction
• The purpose of this switches is to connect currents to
either the inverting or non inverting input of OPAMP
based on the binary inputs given.
• It can closing and opening of the switches based on the
control signal flow.
• These switches are normally operated by digital signals.

• These switching circuits using BJT and MOSFETs.

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 Types of DACs Switches
• Switches using overdriven emitter follower

• Using MOS transistors

– Totem Pole MOSFET switch
– CMOS INVERTER switch

• Switches for multiplying DAC

• Using CMOS transmission gate

• High speed differential switch

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 Switches using Overdriven Emitter
Follower
• Two transistors were connected as emitter followers (common
collector configuration) and it is overdriven to avoid offset
voltage (0.2V for silicon) dropped across them & thus provides
zero offset.

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•• Case
  1: Logic 1 = Switch ON
When = = +5.75 V, is ON and is OFF and (i.e) current passes from +5V supply
to node B through (since it is ON, collector to emitter resistance will be much low).
• Case 2: Logic 0 = Switch OFF

When = = -5.75 V, is ON and is OFF which current passes sink current (from to
-5V supply, thus restricting the current to enter inverting terminal ) of OPAMP.

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 Totem – Pole MOSFET Switch
•• Both
  and are ‘n’ channel enhancement type MOSFETs (‘n’ E-MOSFET). Assume
negative logic system with logic 1 provides -10V and logic 0 provides 0V.
• Before beginning the operation, recall that
– ‘n’ E-MOSFET –ON when Gate = Logic 1 (decrease)
– ‘n’ E-MOSFET – OFF when Gate = Logic 0 ( increase)
Where - drain to source resistance .

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•• Case
  1: Logic 1 input
S=1, R=0,
-ON allowing -10V to appear at Node S
• Case 2: Logic 0 input

S=0, R=1,

-ON allowing -10V to connect to ground

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 CMOS Inverter
•• This
  switch uses two MOSFETs which were enhancement MOSFET
• Before beginning the operation, recall that
– ‘n’ E-MOSFET –ON when Gate = Logic 1 ()
– ‘p’ E-MOSFET – ON when Gate = Logic 0 ()

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•• Case
  1: Logic 1 input ( – Switch ON
, ON (it is PMOS) OFF (it is NMOS) thus connecting the front end resistor
R to +5V supply voltage. The OPAMP Just Act as a buffer and thus the non
inverting terminal second OPAMP connected to low or High voltage
• Case 2: Logic 0 input ( – Switch OFF

, OFF (it is PMOS) ON (it is NMOS) thus connecting the front end resistor
R to ground.

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 Multiplying DAC Switch
•• ,,,  - PMOS
• ,, - NMOS

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•• Logic
  1: is ON and is OFF, therefore current is diverted into the bus
• Logic 0 : is OFF and is ON, therefore current is diverted into the
bus

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 Transmission Gate Switch
•  
• Case 1: Logic 1 input ( – Switch ON

(NMOS) is directly ON and the output of NOT gate is 0 which makes (PMOS) also ON. So the current I
from reference voltage Passes to resistor R through both transistors.
• Case 2: Logic 0 input ( – Switch OFF

(NMOS) is directly OFF and the output of NOT gate is 0 which makes (PMOS) also OFF. So the current
I to enter the resistors R due to high resistance. So simply both transistor were OFF.

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 High Speed Differential Switch
• This is high speed switch and works on differential
configuration. This type of switch is particularly used in
current driven DAC.

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 High Speed Differential Switch
•• Case
  1: Logic 1 input
and thus is ON ( PNP and low bias ) so the bias current passes to the base
of through . So is ON ( It is higher bias current applied to it ). From emitter
of current passes to collector of and thus to (the inverting terminal of
OPAMP).
Case 2: Logic 0 input
and thus is ON so the bias current passes to the base of through . So is
ON and is OFF.Tcurrent passes to collector of and thus to (Normal Ground).
transistor were OFF.

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High Speed Sample and Hold
Circuit
 Introduction
• The circuit which takes samples from the analog input
signal and holds it for a particular period of time is
known as high speed sample and hold circuit.
• This is circuit which has a series switch allowing
samples of input for short duration of time knowing
sampling time.
• This value is holded by a capacitor for holding time.
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 Circuit Diagram

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 Operation
•• The  MOSFET M is used to alternatively connect and disconnect the capacitor to the output
of OPAMP .

• When is ON, the OPAMP and act as voltage follower.

• The capacitor charges or discharge to the value of input signal.

• is at OFF period, The MOSFET M switches OFF and the capacitor holds the value and

retains it until the next sample comes in. time is the acquisition time and is holding time.

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 Waveforms
• During holding time the capacitor
slowly discharges to produce the
change in amplitude ΔV.
• This known as droop.
• To avoid this, capacitor are selected
with less leakage during holding
time.

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