Logic Gates and Boolean

Algebra

Engr. Mia C. Awayan

Instructor
Digital Logic Gates

Ref: Mano, Morris M., Ciletti, Michael D. (2013) Digital Design;

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Logic Gates
Logic gates are electronic circuits that operate on one or
more input signals to produce an output signal.
Electrical signals such as voltages or currents exist as analog
signals having values over a given continuous range, say, 0 to
3 V, but in a digital system these voltages are interpreted to
be either of two recognizable values, 0 or 1.
Voltage‐operated logic circuits respond to two separate
voltage levels that represent a binary variable equal to logic 1
or logic 0.
Ref: Mano, Morris M., Ciletti, Michael D. (2013) Digital Design;
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With an Introduction to the Verilog HDL, 5th Edition, Pearson
Logic Gates
Boolean expression: AND, OR and NOT operations
Constructing gates of other logic operations
• The feasibility and economy;
• The possibility of extending gate's inputs;
• The basic properties of the binary operations
(commutative and associative);
• The ability of the gate to implement Boolean functions.

Ref: Mano, Morris M., Ciletti, Michael D. (2013) Digital Design;

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With an Introduction to the Verilog HDL, 5th Edition, Pearson
Ref: Mano, Morris M., Ciletti, Michael D. (2013) Digital Design;
Logic Gates
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Ref: Mano, Morris M.,Logic Gates
Ciletti, Michael D. (2013) Digital Design;
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With an Introduction to the Verilog HDL, 5th Edition, Pearson
Multiple Inputs
• Extension to multiple inputs
• A gate can be extended to multiple inputs.
• If its binary operation is commutative and associative.
• AND and OR are commutative and associative.
• OR
• x+y = y+x
• (x+y)+z = x+(y+z) = x+y+z
• AND
• xy = yx
• (x y)z = x(y z) = x y z
Ref: Mano, Morris M., Ciletti, Michael D. (2013) Digital Design;
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With an Introduction to the Verilog HDL, 5th Edition, Pearson
Multiple Inputs
• NAND and NOR are commutative but not associative → they are not
extendable.

Demonstrating the nonassociativity of the NOR operator; (x ↓ y) ↓ z

≠ xM.,↓(y
Ref: Mano, Morris ↓ Michael
Ciletti, z) D. (2013) Digital Design;
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With an Introduction to the Verilog HDL, 5th Edition, Pearson
Multiple Inputs
• Multiple NOR = a complement of OR gate, Multiple NAND = a complement of
AND.
• The cascaded NAND operations = sum of products.
• The cascaded NOR operations = product of sums.

Multiple-input and
Ref: Mano, Morris M.,cascated NOR
Ciletti, Michael andDigital
D. (2013) NAND Design;gates
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With an Introduction to the Verilog HDL, 5th Edition, Pearson
Multiple Inputs
• The XOR and XNOR gates are commutative and associative.
• Multiple-input XOR gates are uncommon?
• XOR is an odd function: it is equal to 1 if the inputs variables have an odd
number of 1's.

Ref: Mano, Morris3-input

M., Ciletti,XOR
Michael gate
D. (2013) Digital Design;
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With an Introduction to the Verilog HDL, 5th Edition, Pearson
Positive and Negative Logic
• Positive and Negative Logic
• Two signal values <=> two logic values
• Positive logic: H=1; L=0
• Negative logic: H=0; L=1
• Consider a TTL gate
• A positive logic AND gate
• A negative logic OR gate
• The positive logic is used in this book

Signal
Ref: Mano, Morris M., Ciletti, Michael D. (2013) Digital Design;assignment and logic polarity 11
With an Introduction to the Verilog HDL, 5th Edition, Pearson
Positive and Negative Logic

Ref: Mano, Morris M., Ciletti, Michael D. (2013) Digital Design;

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Demonstration of positive
With an Introduction andHDL,
to the Verilog negative logic
5th Edition, Pearson
Integrated Circuits
Level of Integration
An IC (a chip)
Examples:
Small-scale Integration (SSI): < 10 gates
Medium-scale Integration (MSI): 10 ~ 100 gates
Large-scale Integration (LSI): 100 ~ xk gates
Very Large-scale Integration (VLSI): > xk gates
VLSI
Small size (compact size)
Low cost
Low power consumption
High reliability
High speed
Ref: Mano, Morris M., Ciletti, Michael D. (2013) Digital Design;
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Digital Logic Families
Digital logic families: circuit technology
TTL: transistor-transistor logic (dying?)
ECL: emitter-coupled logic (high speed, high power
consumption)
MOS: metal-oxide semiconductor (NMOS, high
density)
CMOS: complementary MOS (low power)
BiCMOS: high speed, high density
Ref: Mano, Morris M., Ciletti, Michael D. (2013) Digital Design;
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With an Introduction to the Verilog HDL, 5th Edition, Pearson
Digital Logic Families
The characteristics of digital logic families
Fan-out: the number of standard loads that the output of a
typical gate can drive.
Power dissipation.
Propagation delay: the average transition delay time for
the signal to propagate from input to output.
Noise margin: the minimum of external noise voltage that
caused an undesirable change in the circuit output.

Ref: Mano, Morris M., Ciletti, Michael D. (2013) Digital Design;

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CAD
CAD – Computer-Aided Design
Millions of transistors
Computer-based representation and aid
Automatic the design process
Design entry
Schematic capture
HDL – Hardware Description Language
 Verilog, VHDL
Simulation
Physical realization
ASIC, FPGA, PLD

Ref: Mano, Morris M., Ciletti, Michael D. (2013) Digital Design;

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Chip Design
Why is it better to have more gates on a single chip?
Easier to build systems
Lower power consumption
Higher clock frequencies
What are the drawbacks of large circuits?
Complex to design
Chips have design constraints
Hard to test
Need tools to help develop integrated circuits
Computer Aided Design (CAD) tools
Automate tedious steps of design process
Hardware description language (HDL) describe circuits
VHDL (see the lab) is one such system

Ref: Mano, Morris M., Ciletti, Michael D. (2013) Digital Design;

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Binary Logic and Gates
 Binary variables take on one of two values.
 Logical operators operate on binary values and binary variables.
 Basic logical operators are the logic functions AND, OR and
NOT.
 Logic gates implement logic functions.
 Boolean Algebra: a useful mathematical system for specifying
and transforming logic functions.

We study Boolean algebra as a foundation for designing and analyzing digital systems.

Ref: Mano, Morris M., Ciletti, Michael D. (2013) Digital Design;

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With an Introduction to the Verilog HDL, 5th Edition, Pearson
Binary Variables
 Two binary values have different names:
• True/False
• On/Off
• Yes/No
• 1/0
 We use 1 and 0 to denote the two values.
 Variable identifier examples:
 A, B, y, z, or X1 for now
 RESET, START_IT, or ADD1 later

Ref: Mano, Morris M., Ciletti, Michael D. (2013) Digital Design;

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Logical Operations
 The three basic logical operations are:
• AND
• OR
• NOT
 AND is denoted by a dot (·).
 OR is denoted by a plus (+).
 NOT is denoted by an overbar ( ¯ ), a single
quote mark (') after, or (~) before the variable.
Ref: Mano, Morris M., Ciletti, Michael D. (2013) Digital Design;
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Boolean Algebra
 Boolean Algebra is used to analyze and simplify the digital
logic circuits. It uses only the binary numbers i.e. 0 and 1.
 It is also called as Binary Algebra or logical Algebra. It
uses a set of Laws and Rules to define the operation of a
digital logic circuit
 It was invented by George Boole in 1854. In 1938, Claude
E. Shannon introduced a two‐valued Boolean algebra
called switching algebra that represented the properties of
bistable electrical switching circuits.
Ref: Mano, Morris M., Ciletti, Michael D. (2013) Digital Design;
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 Laws of Boolean Algebra
•Annulment
  Law 
• A ● 0 = 0    A variable AND’ed with 0 is always equal to 0
• A + 1 = 1    A variable OR’ed with 1 is always equal to 1
Identity Law 
• A + 0 = A   A variable OR’ed with 0 is always equal to the variable
• A ● 1 = A    A variable AND’ed with 1 is always equal to the variable
Idempotent Law 
• A + A = A    A variable OR’ed with itself is always equal to the variable
• A ● A = A    A variable AND’ed with itself is always equal to the variable
Complement Law 
• A ●   = 0    A variable AND’ed with its complement is always equal to 0
• A +  = 1    A variable OR’ed with its complement is always equal to 1
Ref: Mano, Morris M., Ciletti, Michael D. (2013) Digital Design;
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•Commutative
  Law 
• A ● B = B ● A    The order in which two variables are AND’ed makes no difference
• A + B = B + A    The order in which two variables are OR’ed makes no difference

Double Negation Law 

•= A     A double complement of a variable is always equal to the variable

Distributive Law 
• A(B + C) = A●B + A●C    (OR Distributive Law)
• A + (B●C) = (A + B) ● (A + C)    (AND Distributive Law)
Absorptive Law 
• A + (A●B) = A    (OR Absorption Law)
• A(A + B) = A    (AND Absorption Law)
Ref: Mano, Morris M., Ciletti, Michael D. (2013) Digital Design;
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•Associative
  Law 
• A + (B + C) = (A + B) + C = A + B + C    (OR Associate Law)
• A(B●C) = (A●B)C = A ● B ● C    (AND Associate Law)
De Morgan´s Theorem 
1. Two separate terms NOR´ed together is the same as the two
terms inverted (Complement) and AND´ed for example:   =   ●   
2.Two separate terms NAND´ed together is the same as the two
terms inverted (Complement) and OR´ed for example:   =   +   

Ref: Mano, Morris M., Ciletti, Michael D. (2013) Digital Design;

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With an Introduction to the Verilog HDL, 5th Edition, Pearson
Example
Using the above laws, simplify the expression (A + B)(A + C)
Solution: (A+B)(A+C)

A●A + A●C + A●B + B●C - Distributive Law

A + A●C + A●B + B●C - Idempotent AND law (A●A=A)

A(1 + C) + A●B + B●C - Distributive law

A●1 + A●B + B●C - Identity OR law (1 + C = 1)

A(1 + B) + B●C - Distributive law

A●1 + B●C - Identity OR law (1 + B = 1)

A + B●C - Identity AND law (A●1 = A)

Answer: A + B●C

Ref: Mano, Morris M., Ciletti, Michael D. (2013) Digital Design;

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 Boolean Functions
• A Boolean function
• Binary variables
• Binary operators OR and AND
• Unary operator NOT
• Parentheses
• Examples
• F1= x y z'
• F2 = x + y'z
• F3 = x' y' z + x' y z + x y'
• F4 = x y' + x' z
Ref: Mano, Morris M., Ciletti, Michael D. (2013) Digital Design;
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With an Introduction to the Verilog HDL, 5th Edition, Pearson
Boolean Functions
 The truth table of 2n entries x y z F1 F2 F3 F4
0 0 0 0 0 0 0
0 0 1 0 1 1 1
0 1 0 0 0 0 0
0 1 1 0 0 1 1
1 0 0 0 1 1 1
1 0 1 0 1 1 1
1 1 0 1 1 0 0
1 1 1 0 1 0 0

• Two Boolean expressions may specify the same function

• F3 = F4

Ref: Mano, Morris M., Ciletti, Michael D. (2013) Digital Design;

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With an Introduction to the Verilog HDL, 5th Edition, Pearson
Boolean Functions
• Implementation with logic gates
• F4 is more economical

F2 = x + y'z

F3 = x' y' z + x' y z + x y'

F4 = x y' + x' z

Ref: Mano, Morris M., Ciletti, Michael D. (2013) Digital Design;

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With an Introduction to the Verilog HDL, 5th Edition, Pearson
Algebraic Manipulation
• To minimize Boolean expressions
• Literal: a primed or unprimed variable (an input to a gate)
• Term: an implementation with a gate
• The minimization of the number of literals and the number of terms → a circuit with less
equipment
• It is a hard problem (no specific rules to follow)
• Example 2.1
1.x(x'+y) = xx' + xy = 0+xy = xy
2.x+x'y = (x+x')(x+y) = 1 (x+y) = x+y
3.(x+y)(x+y') = x+xy+xy'+yy' = x(1+y+y') = x
4.xy + x'z + yz = xy + x'z + yz(x+x') = xy + x'z + yzx + yzx' = xy(1+z) + x'z(1+y) = xy +x'z
5.(x+y)(x'+z)(y+z) = (x+y)(x'+z), by duality from function 4. (consensus theorem with duality)

Ref: Mano, Morris M., Ciletti, Michael D. (2013) Digital Design;

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Complement of a Function
• An interchange of 0's for 1's and 1's for 0's in the value of F
• By DeMorgan's theorem
• (A+B+C)' = (A+X)' let B+C = X
= A'X' by theorem 5(a) (DeMorgan's)
= A'(B+C)'substitute B+C = X
= A'(B'C') by theorem 5(a) (DeMorgan's)
= A'B'C' by theorem 4(b) (associative)
• Generalizations: a function is obtained by interchanging AND and OR
operators and complementing each literal.
• (A+B+C+D+ ... +F)' = A'B'C'D'... F'
• (ABCD ... F)' = A'+ B'+C'+D' ... +F'
Ref: Mano, Morris M., Ciletti, Michael D. (2013) Digital Design;
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With an Introduction to the Verilog HDL, 5th Edition, Pearson
Examples
• Example 2.2
• F1' = (x'yz' + x'y'z)' = (x'yz')' (x'y'z)' = (x+y'+z) (x+y+z')
• F2' = [x(y'z'+yz)]' = x' + (y'z'+yz)' = x' + (y'z')' (yz)‘
= x' + (y+z) (y'+z')
= x' + yz‘+y'z
• Example 2.3: a simpler procedure
• Take the dual of the function and complement each literal
1.F1 = x'yz' + x'y'z.
The dual of F1 is (x'+y+z') (x'+y'+z).
Complement each literal: (x+y'+z)(x+y+z') = F1'
2.F2 = x(y' z' + yz).
The dual of F2 is x+(y'+z') (y+z).
Complement each literal: x'+(y+z)(y' +z') = F2'
Ref: Mano, Morris M., Ciletti, Michael D. (2013) Digital Design;
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With an Introduction to the Verilog HDL, 5th Edition, Pearson
Canonical and Standard Forms
Minterms and Maxterms
• A minterm (standard product): an AND term consists of all literals in
their normal form or in their complement form.
• For example, two binary variables x and y,
• xy, xy', x'y, x'y'
• It is also called a standard product.
• n variables con be combined to form 2n minterms.
• A maxterm (standard sums): an OR term
• It is also call a standard sum.
• 2n maxterms.

Ref: Mano, Morris M., Ciletti, Michael D. (2013) Digital Design;

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With an Introduction to the Verilog HDL, 5th Edition, Pearson
Minterms and Maxterms
 Each maxterm is the complement of its corresponding minterm, and vice versa.

Ref: Mano, Morris M., Ciletti, Michael D. (2013) Digital Design;

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With an Introduction to the Verilog HDL, 5th Edition, Pearson
Minterms and Maxterms
• An Boolean function can be expressed by
• A truth table
• Sum of minterms
• f1 = x'y'z + xy'z' + xyz = m1 + m4 +m7 (Minterms)
• f2 = x'yz+ xy'z + xyz'+xyz = m3 + m5 +m6 + m7 (Minterms)

Ref: Mano, Morris M., Ciletti, Michael D. (2013) Digital Design;

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With an Introduction to the Verilog HDL, 5th Edition, Pearson
Minterms and Maxterms
• The complement of a Boolean function
• The minterms that produce a 0
• f1' = m0 + m2 +m3 + m5 + m6 = x'y'z'+x'yz'+x'yz+xy'z+xyz'
• f1 = (f1')'
= (x+y+z)(x+y'+z) (x+y'+z') (x'+y+z')(x'+y'+z) = M0 M2 M3 M5 M6
• f2 = (x+y+z)(x+y+z')(x+y'+z)(x'+y+z)=M0M1M2M4
• Any Boolean function can be expressed as
• A sum of minterms (“sum” meaning the ORing of terms).
• A product of maxterms (“product” meaning the ANDing of terms).
• Both boolean functions are said to be in Canonical form.

Ref: Mano, Morris M., Ciletti, Michael D. (2013) Digital Design;

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With an Introduction to the Verilog HDL, 5th Edition, Pearson
Sum of Minterms
• Sum of minterms: there are 2n minterms and 22n combinations of
function with n Boolean variables.
• Example 2.4: express F = A+BC' as a sum of minterms.
• F = A+B'C = A (B+B') + B'C = AB +AB' + B'C = AB(C+C') + AB'(C+C') +
(A+A')B'C = ABC+ABC'+AB'C+AB'C'+A'B'C
• F = A'B'C +AB'C' +AB'C+ABC'+ ABC = m1 + m4 +m5 + m6 + m7
• F(A, B, C) = S(1, 4, 5, 6, 7)
• or, built the truth table first

Ref: Mano, Morris M., Ciletti, Michael D. (2013) Digital Design;

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With an Introduction to the Verilog HDL, 5th Edition, Pearson
Product of Maxterms
• Product of maxterms: using distributive law to expand.
• x + yz = (x + y)(x + z) = (x+y+zz')(x+z+yy') = (x+y+z)(x+y+z')(x+y'+z)
• Example 2.5: express F = xy + x'z as a product of maxterms.
• F = xy + x'z = (xy + x')(xy +z) = (x+x')(y+x')(x+z)(y+z) = (x'+y)(x+z)(y+z)
• x'+y = x' + y + zz' = (x'+y+z)(x'+y+z')
• F = (x+y+z)(x+y'+z)(x'+y+z)(x'+y+z') = M0M2M4M5
• F(x, y, z) = P(0, 2, 4, 5)

Ref: Mano, Morris M., Ciletti, Michael D. (2013) Digital Design;

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With an Introduction to the Verilog HDL, 5th Edition, Pearson
Conversion between Canonical Forms

• The complement of a function expressed as the sum of minterms equals the

sum of minterms missing from the original function.
• F(A, B, C) = S(1, 4, 5, 6, 7)
• Thus, F'(A, B, C) = S(0, 2, 3)
• By DeMorgan's theorem
F(A, B, C) = P(0, 2, 3)
F'(A, B, C) =P (1, 4, 5, 6, 7)
• mj' = Mj
• Sum of minterms = product of maxterms
• Interchange the symbols S and P and list those numbers missing from the original form
• S of 1's
• P of 0's

Ref: Mano, Morris M., Ciletti, Michael D. (2013) Digital Design;

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With an Introduction to the Verilog HDL, 5th Edition, Pearson
• Example
• F = xy + xz
• F(x, y, z) = S(1, 3, 6, 7)
• F(x, y, z) = P (0, 2, 4, 6)

Ref: Mano, Morris M., Ciletti, Michael D. (2013) Digital Design;

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With an Introduction to the Verilog HDL, 5th Edition, Pearson
Standard Forms
• Canonical forms are very seldom the ones with the least number of
literals.
• Standard forms: the terms that form the function may obtain one, two,
or any number of literals.
• Sum of products: F1 = y' + xy+ x'yz'
• Product of sums: F2 = x(y'+z)(x'+y+z')
• F3 = A'B'CD+ABC'D'

Ref: Mano, Morris M., Ciletti, Michael D. (2013) Digital Design;

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With an Introduction to the Verilog HDL, 5th Edition, Pearson
Implementation
• Two-level implementation

F1 = y' + xy+ x'yz' F2 = x(y'+z)(x'+y+z')

• Multi-level implementation

Ref: Mano, Morris M., Ciletti, Michael D. (2013) Digital Design;

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End..

Ref: Mano, Morris M., Ciletti, Michael D. (2013) Digital Design;

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With an Introduction to the Verilog HDL, 5th Edition, Pearson