DIGITAL SYSTEM DESIGN

LECTURE NO. 2
COURSE OUTLINE
• High-level digital design methodology using VHDL/Verilog, Design, Implementation, and
Verification, Application requiring HW implementation, Floating-Point to Fixed-Point Conversion,
Architectures for Basic Building Blocks, Adder, Compression Trees, and Multipliers,
Transformation for high speed using pipelining, retiming, and parallel processing, Dedicated Fully
Parallel Architecture, Time shared Architecture, Hardwired State Machine based Design, Micro
Program State Machine based Design, FPGA-based design and logic synthesis.
CLOS

• CLO 1: Explain fundamental techniques necessary to design digital systems. (PLO1, C2)
• CLO 2: Design building blocks of digital systems, and employ pipelining, retiming and parallel
processing for their speedup. (PLO3, C6)
• CLO 3: Use hardware descriptive language such as Verilog HDL to design, synthesize and
construct efficient combinational and sequential systems. (PLO5, C6)
• CLO 4: Demonstrate project management skills while designing digital systems. (PLO11, A3)
TEXT BOOK
• T1: Shoab Khan, Digital Design of Signal Processing Systems, 1st edition, 0470741832, John
Wiley & Sons, 2011.

• T2: Michael D. Ciletti, Advanced Digital Design with Verilog HDL, 2nd edition, 0136019282,
Prentice Hall, 2011.

• T3: Samir Palnitkar, Verilog HDL-A guide to Digital Design and Synthesis, 2nd edition,
0132599702, Prentice Hall, 2003.Publisher.
GUIDELINES FOR SYSTEM LEVEL DESIGN FLOW
• A system designer first captures requirements and specifications (R&S) of
the real time system under design.
• Similarly, for digital communication applications, the requirement can be
described in terms of data rates and the communication standard that
modulates this data for transmission
HIERARCHICAL DESIGN

• Verilog works well with a hierarchical

modelling concept. Verilog code contains
a top-level module and zero or more
instantiated modules. The top-level
module is not instantiated anywhere.
Several instantiations of a lower-level
module may exist.
• Ports are used to interconnect instantiated
modules.
• Verilog 2001 support of ANSI style
HIERARCHICAL
DESIGN
SYNTHESIS GUIDELINE
• Avoid Glue Logic (Glue logic is logic that can enable connections from one thing
to another thing. It “glues” two other chips )
• Design Modules with Common Design Objectives
The designer must avoid placing time critical and non time critical logic in the same module
LOGIC VALUES
A bit in Verilog may contain one of four values, as given in Table 2.1
DATA TYPES
Primarily there are two data types in Verilog, nets and registers.
• Nets are physical connections between components. The net data types are wire, tri, wor,
trior, wand, triand, tri0, tri1, supply0, supply1 and trireg. An RTLVerilog code mostly
uses the wire data type. A variable of type wire represents one or multiple bit values.
• A register type variable is denoted by reg. Register variables are used for implicit storage
as values should be written on these variables, and unless a variable is modified it retains
its previously assigned value. Other register data types are integer, time and real.
VARIABLE DECLARATION
• The following syntax is used for declaring a signed wire:

• A similar syntax is used for declaring a signed variable of type reg:

CONSTANTS
• Like variables, a constant in Verilog can be of any size and it can be written in decimal,
binary, octal or hexadecimal format.
FOUR LEVELS OF ABSTRACTION
Verilog provides the designer with the following four levels of abstraction:
• Switch level.
• Gate level.
• Dataflow level.
• Behavioral or algorithmic level.
SWITCH LEVEL
• The lowest level of abstraction is switch or transistor level modeling.
• This level is used to construct gates, though its use is becoming rare as CAD tools
provide a better way of designing and modeling gates at the transistor level.
• A digital design in Verilog is coded at RTL and switch level modeling is not used in RTL,
so this level is not covered in this chapter.
GATE LEVEL OR STRUCTURAL MODELING
• Synthesis tools compile high level code and generate code at gate level.
• The simulation at gate level is very slow compared with the original RTL level code
• The code at gate level is built from Verilog primitives. These primitives are built in gate
level models of basic functions, including nand, nor, and, or, xor, buf and not
• Delays can also be modeled at this level. A typical gate instantiation is
GATE LEVEL MODELING
ANY QUESTION