COMP541

Memories - I

Montek Singh

Mar {21, 23}, 2018

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Topics
 Overview of Memory Types
 Read-Only Memory (ROM): PROMs, FLASH, etc.
 Random-Access Memory (RAM)
 Static today
 Dynamic next

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Types of Memory
 Many dimensions
 Read Only vs. Read/Write (or write seldom)
 Volatile vs. Non-Volatile
 Requires refresh or not

 Look at ROM first to examine interface

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Non-Volatile Memory Technologies
 Mask (old)  ROM
 read-only memory
 Fuses (old)  PROM
 programmable read-only memory
 Erasable  EPROM
 erasable programmable read-only memory
 Electrically erasable  EEPROM
 electrically-erasable programmable read-only memory
 today called FLASH!
 used everywhere!

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Details of ROM
 Memory that is permanent
 k address lines
 2k items
 n bits

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Notional View of Internals
 Main components:
 decoder for address decoding  select one row
 “wired-OR” per bit  OR’s together minterms
 ORing done by connecting outputs of effectively tristate buffers

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Programmed Truth Table

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ROM after programming
 Remember:
 OR is a “wired OR”
 output is 1 if any of the rows with an intact fuse is 1
 0 otherwise

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Mask ROMs
 Oldest technology
 Originally “mask” used as last step in manufacturing
 Specify metal layer (connections)
 Used for volume applications
 Long turnaround
 Used for applications such as embedded systems and, in the
old days, boot ROM

 but cheap to mass produce!

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Programmable ROM (PROM)
 Early ones had fusible links
 High voltage would blow out links
 Fast to program
 Single use

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UV EPROM
 Erasable PROM
 Common technologies used UV light to erase complete device
 Took about 10 minutes
 Holds state as charge in very well insulated areas of the chip
 Nonvolatile for several (10?) years

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EEPROM
 Electrically Erasable PROM
 Similar technology to UV EPROM
 Erased in blocks by higher voltage
 Programming is slower than reading
 Today’s flavor is called “flash memory”
 Digital cameras, MP3 players, BIOS
 Limited life
 Some support individual word write, some block
 Our boards have it:
 A flash memory chip on our Nexys boards
 Has a “boot block” that is carefully protected
 We will learn to use it in upcoming labs

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How Flash Works
 Special transistor with floating gate
 This is part of device surrounded by insulation
 So charge placed there can stay for years
 Aside: some newer devices store multiple bits of info in a cell

 Interested in this?
 Let’s cover briefly

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Flash
 Add an extra gate to an nMOS transistor
 a “float gate” below the actual control gate
 float gate is isolated from everything else
 can hold electrons for a while
 charge on float gate determines bit value stored
 electrons deposited 
negative charge does not allow
transistor to turn on
 if no electrons on float gate 
transistor can be turned on
by the control gate
 two oxide barriers
 between control and floating
gates
 between floating gate and
channel (thin barrier)
https://en.wikipedia.org/wiki/Flash_memory 14
Flash: Reading and Erasing
 Reading
 apply ‘1’ to control gate, and ‘1’ between source and drain
 if floating gate is empty, transistor will be on (current flows)
 if floating gate has electrons, they will mask the control ‘1’
 no current will flow
 Erasing
 apply HIGH negative voltage to
control
 pushes electrons out of floating
gate, through the oxide, into the
channel
 erases the value to ‘1’
 oxide barrier is thin  high
voltage overcomes it
https://en.wikipedia.org/wiki/Flash_memory 15
Flash: Writing
 Writing
 basic idea is to “pull in” electrons into the floating gate,
through the oxide, from the channel
 high voltage needed to pull electrons through oxide barrier
 two methods
 apply HIGH negative voltage to control gate
– pulls electrons from the channel
(via quantum tunneling)
 apply HIGH voltage across channel
(between source and drain), and
a normal ‘1’ to the control
– creates high-velocity electrons
(‘hot electrons’) going
from source to drain
– ‘1’ at the control pulls them
into the floating gate

https://en.wikipedia.org/wiki/Flash_memory 16
Flash: Erasing/Writing speeds
 Erasing/Writing wear
 causes ‘wear’ on the cell
 high voltage used slowly damage the oxide
 often 10,000 erase/write cycles is the limit

 For fast write speeds

 must have empty blocks available
 speeds slows down as memory fills
 thus, garbage collection is important
 overprovisioning used in SSDs

https://en.wikipedia.org/wiki/Flash_memory 17
Read/Write Memories
 Flash is obviously writeable
 But not meant to be written rapidly (say at CPU rates)
 And often writing needs erasure of entire blocks

 For frequent writing, use RAM

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Random Access Memories
 So called because it takes same amount of time to
address any particular location
 Not entirely true for modern DRAMs, but somewhat true…

 First look at asynchronous static RAM

 reading and writing typically controlled by “handshakes”
 clock may still be present, but actions controlled by handshake
signals

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Simple View of RAM
 Typical parameters:
 some word size n
 some capacity 2k
 k bits of address line

 Need a line to specify reading or writing

 typically only one wire needed
 sometimes two separate ones

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Example: 1K x 16 memory
 RAM comes in variety of sizes
 from 1-bit wide
 main issue is no. of pins available
on chip

 Memory size often specified in

bytes
 This would be 2KB memory
 10 address lines (=1K locations)
 16 data lines (=2 bytes/location)

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Writing
 Sequence of steps
 Set up address lines
 Set up data lines
 Activate write line (e.g., maybe a positive edge)

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Reading
 Steps
 Setup address lines
 Activate read line
 Data available soon
 for asynchronous memory: after simply a specified amount of time
 for synchronous memory: after a clock edge

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Chip Select
 Enable:
 Usually a line to enable the chip
 Why?

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Timing: Writing

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Timing: Reading

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Static vs. Dynamic RAM
 Different internal implementations: SRAM vs. DRAM
 DRAM:
 DRAM stores charge in capacitor
 Disappears after short period of time
 Must be refreshed
 Small size
 Higher storage density  larger capacities
 SRAM:
 SRAM easier to use
 Uses transistors (think of it as latch)
 Faster
 More expensive per bit
 Smaller sizes

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Structure of SRAM
 Internally, each bit stored in a “latch”
 One memory cell per bit
 Cell consists of a few transistors
 Not really a latch made of NANDs/NORs, but logically equivalent
 Behaves like an SR latch
 Control logic
 also need extra logic around the latch to make it work like a
memory cell

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Structure of SRAM
 Several optimized circuits often used
 replace a full-fledged SR latch with something simpler,
smaller, faster…
 Not really a latch made of NANDs/NORs, but logically equivalent
 Behaves like an SR latch
 e.g., a simpler 6-transistor memory cell
 wordline  Select
 (bitline, bitline’)  (B, B’) as well as (C, C’)

bitline bitline
wordline

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Example: A Simple Organization
 Note:
 In reality, more complex
 Only one word-line is “on” at a time

2:4
Decoder bitline2 bitline1 bitline0
wordline3
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2 stored stored stored
Address bit = 0 bit = 1 bit = 0
wordline2
10
stored stored stored
wordline1 bit = 1 bit = 0 bit = 0
01
stored stored stored
bit = 1 bit = 1 bit = 0
wordline0
00
stored stored stored
bit = 0 bit = 1 bit = 1

Data2 Data1 Data0

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Zoom in: A single bit slice
 Operation:
 Cells connected to form 1
bit position (column)
 Word Select enables one
latch from address lines
 only this cell is writable
 only this cell is read
 B (and B’) set by:
 Read/Write’
 Data In
 Bit Select
 Outputs are C and C’
 if enabled, output value
of cell
 if disabled, typically
output floating

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Let’s look at a single bit cell

bitline
wordline
stored
bit
Example:
bitline = 0 bitline =Z
wordline = 1 wordline = 0
stored stored
bit = 0 bit = 0

bitline = 1 bitline =Z
wordline = 1 wordline = 0
stored stored
bit = 1 bit = 1

(a) (b)

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Bit Slices and Modules
 Entire column of cells
 called a bit slice
 basically a 1-bit wide memory!
 Module
 module refers to a single chip of
memory
 1-bit wide memory chips are
quite common!

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Inside an SRAM Bit Cell
 Actual implementation does not use a real SR latch!
 a tinier approximation is used
 logically behaves very much like an SR latch
 but much smaller and faster!

bitline
wordline
stored
bit

bitline bitline
wordline

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16 X 1 RAM “Chip”

 Now shows
address decoder
 selects
appropriate
location

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Row/Column Layout
 For larger RAMs:
 decoder becomes pretty big
 also run into chip layout issues

 Typically:
 larger memories use “2D” matrix layout
 see next slide

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16 X 1 RAM as 4 X 4 Array
 Two decoders
 Row
 Column
 Address just
broken up
 Not visible from
outside on
SRAMs

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Not the same as 8 X 2 RAM!
 Minor change in logic
and pins
 Spot the difference!

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Spot the difference!

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Realistic Sizes
 Example: 256Kb memory organized 32K X 8
 Single-column layout would need 15-bit decoder with 32K
outputs!

 Better organization:
 A 2D (i.e., square) layout with:
 9-bit row and 6-bit column decoders

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SRAM Performance
 Latency and Throughput important
 Current ones have cycle times in low nanoseconds
 say 1-2ns (top-end ones even lower)
 Used as cache (typically on-chip or off-chip secondary cache)

 Sizes up to 8Mbit or so for fast chips

 Expensive ones can go a bit bigger

 Energy/power
 SRAMs also better for low power vs. DRAMs

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Wider Memory
 What if you don’t have enough bit width?
 use multiple chips and side-by-side

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Larger/Wider Memories
 Made up from sets of chips
 Consider a 64K by 8 RAM
 our building block

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Larger
 Let’s build a larger
memory
 256K X 8
 Decoder for high-order 2 bits
 Selects chip
 Look at selection logic
 Address ranges
 Tri-state outputs

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Summary
 Today we looked at:
 Quick look at non-volatile memory
 Static RAM

 Next topic:
 Dynamic RAM
 Complex, largest, cheap
 Much more design effort to use

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