Very High Speed Integrated

Circuits Hardware Description

Language
inleiding
VHDL

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 Subjects
 Goal
 Assessments
 Non -appearance
 Subjects
 Plan
 Questions.

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 Goal
 The students are able to describe
hardware with VHDL and to
implement it on a testboard , on their
own

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 Practical
 Following the praktikum is mandatory.
 When you are not able to come please
contact the teacher.
 If you miss more than two practical lessons :
no credits.

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 Assessment
 Theoritical/ practical examination

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 Responsibilities
 The student is responsible for the
hard and software, which must be
used by the next group.
 Defects must be reported immediately

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 Subjects.
 History VHDL
 VHDL Data Types
 VHDL Operators
 VHDL Based Synthesis of Digital Hardware
 Synthesis Models of Gate Networks
 Seven-segment LED Decoder
 Multiplexer
 Tri-State Output
 Flip-flops and Registers
 Inferred Latches
 Counter
 State Machine
 ALU
 Multiply and Divide
 Memory
 Hierarchy

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 Subjects week 1
 History
 Data types
 VHDL operators
 Synthesis
 Gate Networks
 Exercise 1 ‘Adder’
 Introduction Quartus

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 1981 initiation United States Department of Defence
1983-85 baseline language Intermetrics,IBM,IT
1986 rights to IEEE
1987 first publication of IEEE Standard
1994 Revised standard
VHDL(1076-1993)
About each 3 years a new version
2006 new version (more analogue description
possible)
The VHDL standard IEEE 1076-2008[2] was
published in January 2009.

History
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 Alternatives to VHDL
Verilog: biggest next to VHDL

AHDL: Specific to ALTERA company

http://my.ece.msstate.edu/faculty/reese/EE4743/lectures
/verilog_intro_2002/verilog_intro_2002.pdf

Alternatives
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 Variables and Signal types

 Boolean integer real etc

 BIT (IN OUT )
 STD_LOGIC (U, X,0,1,Z,W,L,H,-)
 ‘1’ ‘0’ single quotes 1 bit
 “1001” bitvector

VHDL
Data types
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 STD_LOGIC (U, X,0,1,Z,W,L,H,-)
 'U': uninitialized. This signal hasn't been set yet.
 'X': unknown. Impossible to determine this
value/result.
 '0': logic 0
 '1': logic 1
 'Z': High Impedance
 'W': Weak signal, can't tell if it should be 0 or 1.
 'L': Weak signal that should probably go to 0
 'H': Weak signal that should probably go to 1
 '-': Don't care.

VHDL
Data types
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 STD_LOGIC_VECTOR

 signal t1 : std_logic_vector(7 downto 0);

--7th bit is MSB and 0th bit is LSB

 signal t2 : std_logic_vector(0 to 7); --0th

bit is MSB and 7th bit is LSB here.

 You are free to use both types of

VHDL representations, just have to make sure
that other parts of the design are written
Data types accordingly.
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  Table 1.1 VHDL Operators.


VHDL
Operators
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 ENTITY nand IS
PORT (A,B : IN STD_LOGIC;
Out: OUT STD_LOGIC);
END nand;

ARCHITECTURE behav1 OF nand is

BEGIN
Out <= A NAND B;
END behav1;

ARCHITECTURE behav2 OF nand is

SIGNAL sign : STD_LOGIC;
Gate BEGIN
networks sign <= A AND B;
Out <= NOT sign;
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END behav2;
 Exercise 1
Design a full adder

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 Exercise 2
Design a SR-FLIP FLOP in VHDL

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 Introduction Quartus

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 “Danjel” board

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 “Danjel” board

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 Subjects week 2

 Levels of design
 Behavioral
 Structural
 Register Level
 Timing (chapter4)
 Seven segment decoder(chapter 5)

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 Behavioral level
ARCHITECTURE behavior OF ilatch IS
BEGIN
PROCESS (A, B)
BEGIN
IF A = '0' THEN
Output1 <= '0';
Output2 <= '0';
ELSE
IF B = '1' THEN
Output1 <= '1';
Output2 <= '1';
ELSE
Output1 <= '0'; END
IF;
END IF;
END PROCESS;
END behavior;
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Structural level

architecture structural of BUZZER is

component AND2
port (in1, in2: in std_logic;
out1: out std_logic);
end component;
component OR2
port (in1, in2: in std_logic;
out1: out std_logic);
end component;
component NOT1
port (in1: in std_logic;
out1: out std_logic);
end component;
signal DOOR_NOT, SBELT_NOT, B1, B2: std_logic;
begin
U0: NOT1 port map (DOOR, DOOR_NOT);
U1: NOT1 port map (SBELT, SBELT_NOT);
U2: AND2 port map (IGNITION, DOOR_NOT, B1);
U3: AND2 port map (IGNITION, SBELT_NOT, B2);
13-04-21 U4: OR2 port map (B1, B2, WARNING); 23
end structural;
 RTL level design
architecture BEHAV_DFF of DFF_CLEAR is
begin
DFF_PROCESS: process (CLK, CLEAR)
begin
if (CLEAR = ‘1’) then
Q <= ‘0’;
elsif (CLK’event and CLK = ‘1’) then
Q <= D;
end if;
end process;
end BEHAV_DFF;
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 Time level descriptions

ARCHITECTURE behavior OF gate_network IS

BEGIN
X <= A AND NOT(B OR C) AND (D(1) XOR D(2)) after 10 ns;
PROCESS (A,B,C,D)
BEGIN
Y <= A AND NOT(B OR C) AND (D(1) XOR D(2))after 20 ns;
END PROCESS;
END behavior;

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 Explicite processes ,
The Sensitivity list
compute_xor: process (b,c)
begin
a<=b xor c;
end process;
compute_xor: process (c)
begin
a<=b xor c;
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end process;http://esd.cs.ucr.edu/labs/tutorial/ 26
 implicite processes
In inplicit processes you do not see the
word “process”. Each assignment is a
process on itself

begin
a<=b xor c;
d<=b and c;

end archx;
13-04-21 http://esd.cs.ucr.edu/labs/tutorial/ 27
7 segments
decoder
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 Architecture with case statement
ARCHITECTURE behaviour OF sevensegm
PROCESS(msd)
BEGIN
CASE msd IS
WHEN “0000” =>
msd_7seg <= “1111110”;

7 segments WHEN “0000” =>

decoder msd_7seg <=“0110000”;

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etc 29
 Assignment 1,2
Write a structural architecture of the next schematics;

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 Assignment 3
architecture structural_2 of multiplexer_4_to_1_st is
component NOT1 port( in1 : in std_logic; out1 : out
std_logic); end component;

component AND3 port( in1, in2, in3 : in std_logic; out1

out std_logic); end component;

component OR4 port( in1, in2, in3, in4 : in std_logic;

out1 : out std_logic); end component;
signal S_n : std_logic_vector(0 to 1);
signal N : std_logic_vector(0 to 3);
begin
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 Assignment 3
begin
g0: NOT1 port map (S(0), S_n(0));
g1: NOT1 port map (S(1), S_n(1));
g2: AND3 port map (S_n(1), S_n(0), D(0), N(0));
g3: AND3 port map (S_n(1), S(0), D(1), N(1));
g4: AND3 port map (S(1), S_n(0), D(2), N(2));
g5: AND3 port map (S(1), S(0), D(3), N(3));
g6: OR4 port map (N(0), N(1), N(2), N(3), Y);
end structural_2;

Asked: draw schematic and

write an alternative in
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behavioural VHDL 32
 Excersises (week 2)
 Do the self test of chapter 3,4,5,
 Read chapter 3,4,5,4,5
 Do self test chapter 3,4,5
 Prepare the practical work of chapter
3 ,4 and 5

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 Subjects week 3
 Multiplex and demultiplex(Chapter 6)
 Tri state (Chapter 7)
 Flip-flops and registers(Chapter 8)

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 Mux_out <=A WHEN Mux_Control =‘0’
ELSE Mux_out <=B;

Multiplexer
when else

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 Process(A,B,Mux_control)
begin
if Mux_control =‘0’ then Mux_out <=A
Multiplexer
if else Mux_out <= B; end if;
end process;
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 Process(A,B,Mux_control)
Begin
case Mux_control is
when ‘0’ =>
mux_out <= A;
when ‘1’=>
mux_out <= B;
when others =>
Multiplexer mux_out <= A;
case end case;
end process;

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 ENTITY tristate IS
PORT(A,Control : IN STD_LOGIC;
Tri_out :INOUT STD_LOGIC);
END tristate;

Tri-State
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 ARCHITECTURE behaviour OF tristate IS
BEGIN
Tri_out <= A WHEN Control =‘0’ ELSE ‘Z’;
END behaviour;

Tri-State 2 FOR SYNTHESIS LOOK IF YOUR

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 flipflops and registers

in VHDL you have many possibilties to

implement flipflops. Also the different
ff as jk and rs can be implementet. But
using FPGA , most of the time there
are already d-ff implemented.
Therefore we always use d-ff.

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 D-Flip flop

-- Positive edge triggered D flip-flop

-- If WAIT is used no sensitivity list is used
PROCESS
BEGIN
WAIT UNTIL (Clock'EVENT AND Clock='1');
Q1 <= D;
END PROCESS;

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 Gated D-Flip flop

PROCESS (Reset,Clock)
BEGIN
IF reset = '1' THEN
Q4 <= '0';
ELSIF (clock'EVENT AND clock='1') THEN
IF Enable = '1'
THEN Q4 <= D;
END IF;
END IF;
END PROCESS;

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 Gated D-ff register

PROCESS (Reset,Clock)
BEGIN
IF reset = '1' THEN
Q4 <= '00000000';
ELSIF (clock'EVENT AND clock='1') THEN
IF Enable = '1'
THEN Q4 <= D;
END IF;
END IF;
END PROCESS;

13-04-21 How is the entity described? 43

 Case statement example
process(a)
begin
case a is
when "00" => b <= "1000";
when "01" => b <= "0100";
when "10" => b <= "0010";
when "11" => b <= "0001";
when others => report
"unreachable" severity failure;
end case;
end process
How is the entity described?
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 Assignment week 3

•Do self test chapter 7,8

•Do the exercises chapter 6,7,8

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 Subjects week 4
 Inferred latches(Chapter 9)
 Counters (Chapter 10)
 Simulating with Quartus simulator
 FPGA MAX II technology
 LUT
 I/O

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 Accidental Synthesis of inferred
latch
ARCHITECTURE behavior OF ilatch IS
BEGIN
PROCESS (A, B)
BEGIN
IF A = '0' THEN
Output1 <= '0';
Output2 <= '0';
ELSE
IF B = '1' THEN
Output1 <= '1';
Output2 <= '1';
ELSE
Output1 <= '0'; --latch inferred
since no
-- value is assigned to output 2 in the else clause
END IF;
END IF;
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END PROCESS; 47
END behavior;
 Counters
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;

internal_count <= internal_count + 1;

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 Counters
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Counter2_VHDL is
port( Clock_enable_B: in std_logic;
Clock: in std_logic;
Reset: in std_logic;
Output: out std_logic_vector(0 to 3));
end Counter2_VHDL;

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Counters architecture Behavioral of Counter2_VHDL is
signal temp: std_logic_vector(0 to 3);
begin
process(Clock,Reset)
begin
if Reset='1‘
then temp <= "0000";
elsif(Clock'event and Clock='1')
then if Clock_enable_B='0'
then if temp="1111"
then temp<="0000";
else temp <= temp + 1;
end if;
end if;
end if;
end process;
13-04-21 Output <= temp; 50
end Behavioral; 50
Simulating with Quarter simulator (1) 4 to 1

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51
Simulating with Quarter simulator
(up/down counter)

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52
 FPGA MAX II technology (1)

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53
FPGA MAX II technology (2)

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54
 Look Up Table (LUT)

A LUT can be programmed so that it can

contain any type of logic function.

Each logic block can only store small

functions of several variables.

A LUT may be used as:

•A random combinatorial circuit with up to 4
inputs
•16-bit memory
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55
 Look Up Table (LUT)

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56
13-04-21 57
57
I/O FEATURES
IOEs support many features, including:
■ LVTTL and LVCMOS I/O standards
■ 3.3-V, 32-bit, 66-MHz PCI compliance
■ Weak pull-up resistors during power-up and in system
programming
■ Slew-rate control
■ Tri-state buffers with individual output enable control
■ Programmable pull-up resistors in user mode
■ Unique output enable per pin
■ Open-drain outputs
■ Schmitt trigger inputs
■ Programmable Drive Strength

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58
I/O FEATURES

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59
 Subjects week 5
 Statemachines(Chapter 11)
 ALU (Chapter 12)
 Multiply (Chapter 13)
 Memory (Chapter 14)

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 State Machines

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State Machines (flow)
library IEEE;
use IEEE.STD_LOGIC_1164.all;
ENTITY st_mach IS
PORT( clk, reset : IN STD_LOGIC;
Input1, Input2 : IN STD_LOGIC;
Output1 : OUT STD_LOGIC);
END st_mach;

ARCHITECTURE A OF st_mach IS
-- Enumerated Data Type for State
TYPE STATE_TYPE IS (state_A, state_B, state_C);
SIGNAL state: STATE_TYPE;
BEGIN
PROCESS (reset, clk)
BEGIN
IF reset = '1' THEN
state <= state_A;
ELSIF clk'EVENT AND clk = '1' THEN
CASE state IS
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State Machines
ELSIF clk'EVENT AND clk = '1' THEN
CASE state IS
WHEN state_A =>
IF Input1 = '0' THEN
state <= state_B;
ELSE
state <= state_C;
END IF;
WHEN state_B =>
state <= state_C;
WHEN state_C =>
IF Input2 = '1' THEN
state <= state_A;
END IF;
WHEN OTHERS =>
state <= state_A;
END CASE;
END IF;
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END PROCESS;
State Machines (output decoder)

PROCESS (state)
BEGIN
CASE state IS
WHEN A =>
output1 <= ‘0';

WHEN B =>
output1 <= '1';
WHEN C =>
output1 <= ‘0';
END CASE;

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VHDL Synthesis Model of an ALU ALU

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65
12. VHDL Synthesis Model of an ALU
library and entity
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;

ENTITY ALU IS
PORT(
Op_code : in std_logic_vector(2 DOWNTO 0);
A_input, B_input: in std_logic_vector(7 DOWNTO 0);
ALU_output : out std_logic_vector(7 DOWNTO 0));
 
END ALU;

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VHDL Synthesis Model of an ALU A
architecture ARCHITECTURE behavior OF ALU IS
-- declare signal(s) internal to module here
SIGNAL temp_output: std_logic_vector(7 DOWNTO 0);
BEGIN
PROCESS (Op_code, A_input, B_input)
BEGIN
-- Select Arithmetic/Logical Operation
CASE Op_Code (2 DOWNTO 1) IS
WHEN "00" =>
temp_output <= A_input + B_input;
WHEN "01" =>
temp_output <= A_input - B_input;
WHEN "10" =>
temp_output <= A_input AND B_input;
WHEN "11" =>
temp_output <= A_input OR B_input;
WHEN OTHERS =>
temp_output <= "00000000";
END CASE;
-- Select Shift Operation
IF Op_Code(0) = '1' THEN
-- Shift bits left with zero fill using concatination operator
-- can also use VHDL 1076-1993 shift operator such as SLL
Alu_output <= temp_output(6 DOWNTO 0) & '0';
ELSE
Alu_output <= temp_output;
END IF;
13-04-21 END PROCESS; 67
END behavior;
VHDL Synthesis Model of multiply and
Divide hardware
-Efficient design requires vendor

specific library function

-Use MegaWizard in Quartus
- Foating point operations needs

big FPGA, flp DSP and

microprocessors have a better
performance
-- Special functions are available , for

13-04-21 example Digital filtering 68

VHDL Synthesis Model of multiply and
Divide hardwareALU
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
LIBRARY lpm;
USE lpm.lpm_components.ALL;
 
ENTITY mult IS
PORT( A,B : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
Product : OUT STD_LOGIC_VECTOR(15 DOWNTO 0));
END mult;
 
ARCHITECTURE a OF mult IS
BEGIN
multiply: lpm_mult
GENERIC MAP( LPM_WIDTHA => 8,
LPM_WIDTHB => 8,
LPM_WIDTHS => 16,
LPM_WIDTHP => 16,
LPM_REPRESENTATION => "UNSIGNED")
PORT MAP ( dataa => A,
datab => B,
13-04-21 result => Product); 69 69
END a;
VHDL Synthesis models for memory
LIBRARY IEEE;
USE IEEE.STD_LOGIC1164.ALL;
 
ENTITY amemory IS
PORT(read_data :OUT STD_LOGIC_VECTOR( 7 DOWNTO 0 );
memory_address : IN STD_LOGIC_VECTOR( 2 DOWNTO 0 );
write_data :IN STD_LOGIC_VECTOR( 7 DOWNTO 0 );
Memwrite :IN STD_LOGIC;
Clock,reset : IN STD_LOGIC );
END amemory;
 
ARCHITECTURE behavior OF amemory IS
BEGIN
Data_memory:lpm_ram_dq --LPM memory function
 
GENERIC MAP (lpm_widthad =>3,
lpm_outdata =>”UNREGISTERED” ¸
lpm_indata =>”REGISTERED”¸
lpm_address_control =>”UNREGISTERED” ¸

PORT MAP (data => write_data, address => memory_address( 2 DOWNTO 0 ),

We => Memwrite, inclock => clock, q =>read_data );
END behavior;

 
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VHDL Synthesis LIBRARY IEEE; models for memory example
2 USE IEEE.STD LOGIC 1164.ALL;
ENTITY memory IS
PORT( read data : OUT STD_LOGIC_VECTOR( 7 DOWNTO 0 );
read address : IN STD_LOGIC_VECTOR( 2 DOWNTO 0 );
write-data : IN STD_LOGIC_VECTOR( 7 DOWNTO 0 );
write address : IN STD_LOGIC_VECTOR( 2 DOWNTO 0 );
Memwrite : IN ST_ LOGIC;
Clock : IN STD_LOGIC );
END memory;
 
ARCHITECTURE behavior OF memory IS
define new data type for memory array
TYPE memory_type IS ARRAY ( 0 TO 7 ) OF STD_LOGIC_VECTOR (7 DOWNTO 0 );
SIGNAL memory : memory type;
BEGIN
--Read Memory and convert array index to an integer with CONV INTEGER
read-data <= memoir (CONV_INTEGER )read-address (2 downto 0 ) );
PROCESS - - Write Memory?
BEGIN
WAIT UNTIL clock 'EVENT AND clock = '1';
IF ( memorize = '1' ) THEN
--- convert array index to an integer with CONV INTEGER
memory ( CONV_INTEGER) write-address( 2 DOWNTO 0 ) ) ) <= write-data;
END IF;
13-04-21 END PROCESS; 71
71
END behavior;
 Subjects week 6
 Hierarchy (Chapter 15)
 Explanation final assignments

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15 Hierarchy in VHDL Synthesis models

-Large VHDL models :Split

-Use graphic editors
-Split to: write, understand ,maintain

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15 Final assignment Moving average filter

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Draw a blockschemtic. 74 74
15 Final assignment Serial send (9600 baud)

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Source : pic16f690 datasheet microchip
17 Conclusion
•Just an introduction of VHDL
basics
•Many templates and examples

IEEE
•Many online examples

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