Chapter 4

Combinational Logic

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 Outline
4.1. Combinational Circuits
4.2. Analysis Procedure
4.3. Design Procedure
4.4. Binary Adder-Subtractor
4.5. Decimal Adder
4.6. Binary Multiplier
4.7 Magnitude Comparator
4.8. Decoders
4.9. Encoders
4.10.Multiplexers

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 4.1. Combinational Circuits

A combinational circuit consists of logic gates whose

outputs at any time are determined from only the
present combination of inputs.

The diagram of a combinational circuit has logic gates with

no feedback paths or memory elements .

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 4.4. Binary Adder-Subtractor
 Half Adder

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 4.4. Binary Adder-Subtractor
 Half Adder

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 Binary Adder-Subtractor
 Full Adder

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 Binary Adder-Subtractor
 Full Adder

Simplify!

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 Binary Adder-Subtractor
 Full Adder

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 Binary Adder-Subtractor

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 Binary Adder-Subtractor

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 Binary Adder-Subtractor

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 Binary Adder-Subtractor
 Binary Adder

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 Binary Adder-Subtractor
 Binary Adder

Ripple Carry Adder

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 Binary Adder-Subtractor
 Carry Propagation

Gi is called a carry generate

Pi is called a carry propagate

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 Binary Adder-Subtractor
 Carry Propagation

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 Binary Adder-Subtractor
Carry Propagation

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 Binary Adder-Subtractor

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 Binary Subtractor

Make a binary Subtractor

5 Minutes for the Task!

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 Binary Subtractor

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 OverFlow
When two numbers with n digits each are added and the sum is a
number occupying n + 1 digits, we say that an overflow occurred.

In digital computers because the number of bits that hold the number
is finite and a result that contains n + 1 bits cannot be accommodated
by an n -bit word.

When two unsigned numbers are added, an overflow is detected from

the end carry out of the most significant position

Signed Numbers

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 OverFlow

Signed Numbers

0 1 1 0

1 1

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 4.5. Decimal Adder
Add 0110
 BCD Adder

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 4.5. Decimal Adder

BCD Adder

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 4.6. Binary Multiplier

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 4.6. Binary Multiplier

J Multiplier bits
K Multiplicand bits

J x K AND gates
(J-1) K-bit adders

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 Binary Multiplier

B3B2B1B0 Multiplicand bits (K)

A2A1A0 Multiplier bits (J)

J x K AND gates
(J-1) K-bit adders

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 4.7 Magnitude Comparator
 A magnitude comparator is a
combinational circuit that compares two
numbers A and B and determines their
relative magnitudes.
 The outcome of the comparison is specified
by three binary variables that indicate whether
A > B, A = B, or A < B.

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 4.7 Magnitude Comparator

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 4.8. Decoders
 A binary code of n bits is capable of
representing up to 2n distinct elements of
coded information.
 A decoder is a combinational circuit that
converts binary information from n input
lines to a maximum of 2n unique output
lines.
 If the n-bit coded information has unused
combinations, the decoder may have fewer
than 2n outputs.
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 4.8. Decoders

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 4.8. Decoders

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 4.8. Decoders

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 Decoders

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 Combinational Logic Implementation

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 Combinational Logic Implementation

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 4.9. Encoders
 Performs an inverse function of a decoder.
 Encoder has 2n input lines
 Has n output lines

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 4.9. Encoders
 Performs an inverse function of an
decoder.
 Encoder has 2n input lines
 Has n output lines

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 Priority Encoder
 A priority encoder is an encoder circuit that
includes the priority function.
 The operation of the priority encoder is such that
if two or more inputs are equal to 1 at the same
time, the input having the highest priority will take
precedence
 The circuit has a third output designated by V ;
this is a valid bit indicator that is set to 1 when
one or more inputs are equal to 1.
 If all inputs are 0, there is no valid input and V is
equal to 0.

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 Priority Encoder

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 Priority Encoder

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 Priority Encoder

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 4.10.Multiplexers
 A multiplexer is a combinational circuit that
selects binary information from one of many
input lines and directs it to a single output line.
 The selection of a particular input line is
controlled by a set of selection lines
 Normally, there are 2n input lines and n selection
lines whose bit combinations determine which
input is selected

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 4.10.Multiplexers

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 4.10.Multiplexers

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 4.10.Multiplexers

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 Make a 4x1 Multiplexer
using two 2x1 Multiplexers

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 Verilog Modules of Combination Logic
 Gate-level modeling using instantiations of
predefined and user-defined primitive
gates.
 Gate-level (structural) modeling describes a
circuit by specifying its gates and how they
are connected with each other.

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 Verilog Modules of Combination Logic
 Dataflow modeling using continuous
assignment statements with the keyword
assign .
 Dataflow modeling is used mostly for
describing theBoolean equations of
combinational logic.

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 Verilog Modules of Combination Logic
 Behavioral modeling using procedural
assignment statements with the keyword
always .

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 Gate-Level Modeling

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 Ripple Carry Adder

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 Three-State Gates

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 Dataflow: Two-to-Four Line Decoder

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 DataFlow

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 Dataflow: Conditional Operator

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 Behavioral Modeling

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 Behavioral Modeling

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 TestBench

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 TestBench

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