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Shift Register
Shift Register
Roger L. Tokheim
Chapter 9
Shift Registers
©1999 Glencoe/McGraw-Hill
CHAPTER 9 PREVIEW
• Overview of Shift Registers
• Characteristics of Shift Registers
• Serial/Parallel Data Conversion
• Serial Load Shift Register
• Parallel Load Shift Register
• Recirculating Shift Register
• Using the 74194 Shift Register IC
• Digital Roulette Game
• Troubleshooting Hints
OVERVIEW OF
SHIFT REGISTERS
• A shift register is a sequential logic device
made up of flip-flops that allows parallel or
serial loading and serial or parallel outputs
as well as shifting bit by bit.
• Common tasks of shift registers:
– Serial/parallel data conversion
– UART (an example)
– Time delay
– Ring counter
– Twisted-ring counter or Johnson counter
– Memory device
CHARACTERISTICS OF
SHIFT REGISTERS
•Number of bits (4-bit, 8-bit, etc.)
•Loading
– Serial
– Parallel (asynchronous or synchronous)
•Common modes of operation.
– Parallel load
– Shift right-serial load
– Shift left-serial load
– Hold
– Clear
•Recirculating or non-recirculating
SERIAL/PARALLEL
DATA CONVERSION
Shift registers can be used to convert from serial-
to-parallel or the reverse from parallel-to-serial.
Parallel out
Parallel out
11 0 11 00 11 11 11 11 Serial out
Serial in 0
1 0 1 0 1 1 1 1 Serial out
Parallel in
SERIAL LOAD SHIFT REGISTER
Parallel outputs here.
Order= A B C D
1 1
0 0 0
1 0
1
Data =
Data =01
Inputs here: 4-bit
Clock input: serial-in
(1) Data Clock Pulse 2
Positive-edge
Clock Pulse 1
3
4
6
7
5
8 parallel out
(2) Clock
Clear input:
triggering shift right
(3) Clear
Active = 0 =1
Clear 0 shift register
Deactivated = 1
Data
Data =
Data
Data ==1
1
00
1
Clock
Clock
ClockPulse
Clock Pulse
Pulse
Pulse26
4
13
5
Clear
Clear =
Clear
Clear ==1
01
1
PARALLEL LOAD SHIFT REGISTER
Outputs here.
Order= A B C D
Parallel data
inputs
(Active LOW)
Recirculating
lines:
Clock input- H-to-L Pass data
Note thefrom
FFD to FFA
recirculating
on each
lines.
Clear input- Active LOW clock pulse.
Clock
Clockpulse
pulse8 7
1
2
3
5
6
4
Clear
Clearinput=
input=1 0
1
UNIVERSAL SHIFT REGISTER IC
Outputs here
Clear input
Serial data Rightactive
input LOW
used during
Serial Load Right
mode ofdata
Parallel operation
inputs
Order: A, B, C, D
during data
Serial Leftloading
Parallel input
used during
Serial Load Left
mode of operation
Clock input
Mode
L-to-HControls:
triggering
Hold
Parallel load
Shift right
Shift left
Serial R = X
0
Parallel Load=
01010
Serial L = 0
X
1
Clock pulse 8
1
2
3
4
5
6
7
(L-to-H)
S0= 0
1
S1= 1
0
X = Irrelevant
TEST
QUESTION
QUESTION#3 #1
#2
#5
#6
#7
QUESTION #4- What is the mode of operation during and the output of the
The
What
What74194
isisthe
the
IC
mode
mode
could
of
ofbe
operation
operation
described
during
during
as a 4-bit
and
andthe
the
(shift
output
output
right,
ofof
universal)
the
the
shift register after pulse 3?
shift
shiftregister
register.
registerafter
afterpulse
pulse2?
1?
4?
5?
6?
A:A:A:A: A:right,
Parallel
A:
Shift
Shift
Clear,
Hold,Universal
left,
load,
00001
0001
0
0010
1
101
00
? ? ? ?
CLR =
CLR =10
1
X
Serial R = 0
Parallel Load=
Parallel Load=
01
0 10
00 0
Serial L = X
1
1
2
4
Clock pulse 6
3
5
(L-to-H)
(L-to-H)
1
S0= 0
0
S1= 1
DIGITAL ROULETTE GAME
Audio
Amplifier
1
0
0
1
0 1
0
Power-up
Initializing 0
1 1
0
Spin Circuit
Wheel 1
0 1
0
1
0
+5V input
Voltage
8-bit Simulated
Controlled
Ring Counter Roulette
Oscillator
(shift register) Display
(VCO)
SIMPLE TROUBLESHOOTING HINTS