Implementation

strategies
MODULE OVERVIEW
� Processors
� ASIC’s
� Types of ASIC’s
� ASIC cell library

EC6601 VLSI Design Prof.B.Sathyabhama

 A SIMPLE PROCESSOR

MEMORY

INPUT/ CONTROL
OUTPUT

DATAPATH

EC6601 VLSI Design Prof.B.Sathyabhama

 IMPLEMENTATION CHOICE

Digital Circuit Implementation Approaches

Custom Semicustom

Cell Based Array Based

Pre-diffused Pre-wired
Standard cell
Macro cell (Gate array) (FPGA)
Compiled cell
4

EC6601 VLSI Design Prof.B.Sathyabhama

 ASIC VS STANDARD IC
❑ Standard ICs – ICs sold as Standard Parts
❖ SSI/LSI/ MSI IC such as MUX, Encoder, Memory Chips, or Microprocessor IC

❑ Application Specific Integrated Circuits (ASIC)

❖ A Chip for Toy Bear, Auto-Mobile Control Chip, different communication Chips.
❖ Concept Started in 1980s
❖ An IC Customized to a Particular System or Application - Custom ICs
❖ Digital designs became a matter of placing of fewer ICs or ASICs + some Glue Logic
❖ Reduced Cost and Improved Reliability

❑ Application Specific Standard Parts (ASSP)

❖ Controller Chip for PC or a Modem

EC6601 VLSI Design Prof.B.Sathyabhama

 TYPES OF ASICS
ASICs

Full-Custom Semi-Custom
ASICs ASICs

Standard cell Gate Array Programmable

based ASICs based ASICs ASICs

PLDs FPGA

EC6601 VLSI Design Prof.B.Sathyabhama

 Full-Custom ASICs:
Possibly all logic cells and all mask layers
customized

Semi-Custom ASICs:
All logic cells are pre-designed and some
(possibly all) mask layers customized

EC6601 VLSI Design Prof.B.Sathyabhama

 Full-Custom ICs
� Full-custom design is a methodology for designing integrated circuits by specifying the
layout of each individual transistor and the interconnections between them. 

� Full-custom design potentially maximizes the performance of the chip, and minimizes its area,
but is extremely labor-intensive to implement. 

� Full-custom design is limited to ICs that are to be fabricated in extremely high volumes, such
as in microprocessors

� Time taken to design IC is longer and slow

� It includes some logic cell and mask layers that are customized

� Therefore, IC’s are most expensive to manufacture and design 8

� Ex: Microprocessor
EC6601 VLSI Design Prof.B.Sathyabhama
 FULL CUSTOM DESIGN FLOW

specification

Algorithm/
Architecture

Circuit Level SPICE Simulation

Design

Layout DRC/LVS

Fabrication
9

EC6601 VLSI Design Prof.B.Sathyabhama

 SEMI-CUSTOM ASICS
� Semi-custom IC design is a methodology for making an integrated circuit which a portion of the
circuit function is predefined and unalterable, while other portions can be configured to meet the
designer's specific needs.

� Designers have the capability of designing application-specific circuits themselves, using either
standard cell libraries or preconfigured arrays.

� Insemicustom IC, all of the logic cells are predesigned and some (possibly all) of the mask
layers are customized.

� Therefore,
semi-custom ICs are the less expensive to manufacture and to design.
Examples : Ethernet chip, hard disk controller

� Semi custom IC design are classified as two types

1. Cell based 10
2. Array based
EC6601 VLSI Design Prof.B.Sathyabhama
 STANDARD CELL BASED ASIC’S

Standard
Cell area
1

2 3

Fixed
block 4 5

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EC6601 VLSI Design Prof.B.Sathyabhama

 GATE ARRAY BASED ASICS
� A gate array based ASIC has predefined transistors on the silicon
wafer, the predefined pattern of transistors on a gate array is the
base array.
� The base array is made up of the smallest element called a
primitive cell.
� The top few layers of metals are defined using custom masks,
which is called as Masked Gate Array (MGA).
� The logic cells in a gate array library are called macros.
� There are three types of gate arrays.
❖ Channeled gate arrays
❖ Channelless gate arrrays
12
❖ Structured gate arrays
EC6601 VLSI Design Prof.B.Sathyabhama
 contd
Channeled gate array:
❖ Only the interconnect is customized
❖ The interconnect uses predefined
spaces between rows of base cells.
EC6601
Channelless gate array
(Channel-free gate array, sea
of gate array or SOG array):
❖ Only some mask layers are
customized
❖ Manufacturing lead time is
between two days and two weeks.
13
VLSI Design Prof.B.Sathyabhama
 contd
Embedded gate array or structured gate array (masterslice or
masterimage)
� Only the interconnect is customized
� Custom block can be embedded
� Manufacturing lead time is between two days and two weeks.

14

EC6601 VLSI Design Prof.B.Sathyabhama

 PROGRAMMABLE LOGIC DEVICE
� Programmable Logic Device
⚫ Programmable Logic Array, Programmable Array Logic, Field
Programmable Gate Array
� All layers already exist
⚫ Designers can purchase an IC
⚫ To implement desired functionality
�Connections on the IC are either created or destroyed to implement
Benefits
⚫ Very low NRE costs
⚫ Great time to market
Drawback
⚫ High unit cost, bad for large volume
⚫ Power 15
�Except special PLA
EC6601 VLSI Design Prof.B.Sathyabhama
 LIBRARIES
� A standard cell library is a collection of low-level
electronic logic functions such as AND, OR, INVERT,
flip-flops, latches, and buffers.
� The cells are typically optimized full-custom layouts,
which minimize delays and area.
� A typical standard-cell library contains two main
components:
⚫ Library Database : Consists of a number of views often including
layout, schematic, symbol, abstract, and other logical or simulation views
⚫ Timing Abstract : Generally in library format to provide functional
definitions, timing, power, and noise information for each cell.
16

EC6601 VLSI Design Prof.B.Sathyabhama

 contd
� A standard-cell library may also contain the following
additional components:
⚫ A full layout of the cells
⚫ Spice models of the cells
⚫ Verilog models or VHDL – VITAL models
⚫ Parasitic Extraction models
⚫ DRC rule checks
o An example is a simple  XOR logic gate, which can be formed from OR, INVERT
and AND gates.

17

EC6601 VLSI Design Prof.B.Sathyabhama

 STANDARD CELL LIBRARY
FORMATS
� Standard cell libraries are required by almost all CAD tools for
chip design
� Standard cell libraries contain primitive cells required for digital
design. However, more complex cells that have been specially
optimized can also be included
� The main purpose of the CAD tools is to implement
RTL(register transfer level ) -to-GDS (Gerber data stream) flow
� The input to the design process, in most cases, is the circuit
description at RTL
� The final output from the design process is the full chip layout,
18
mostly in the GDSII (gds2) format
EC6601 VLSI Design Prof.B.Sathyabhama
 FLOW CHART FOR STANDARD CELL
DESIGN
Initial design Layout design

Estimated result Yes Extraction result

No

No
Redesign Compare
result

Yes

Finish
19

EC6601 VLSI Design Prof.B.Sathyabhama

 SEMICUSTOM DESIGN FLOW
Design capture Behavioral

HDL
Pre layout
simulation
Logic synthesis Structural
iteration

Floor planning
Design

Post layout physical

simulation
placement

Circuit extraction Routing

Tape out 20

EC6601 VLSI Design Prof.B.Sathyabhama

FPGA’S
 FIELD-PROGRAMMABLE GATE
ARRAYS
� Xilinx FPGAs are based on Configurable Logic Blocks (CLBs)
� More generally called logic cells
� Programmable

CLB

I/O blocks
not shown 22

EC6601 VLSI Design Prof.B.Sathyabhama

 FPGA INTERNAL
ARCHITECTURE

23

EC6601 VLSI Design Prof.B.Sathyabhama

 CONTD

� Logic blocks of an FPGA can be implemented

by any of the following.
�Transistor pairs
�Combinational gates like basic NAND gates or Xor gates
�N-input lookup tables
�Multiplexers
�Wide fan-in AND-OR structure

24

EC6601 VLSI Design Prof.B.Sathyabhama

 FPGA STRUCTURAL
CLASSIFICATION

On basis of internal arrangement of blocks

FPGA’s can be divided into three classes

1.Symmetrical arrays
2.Row based architecture
3.Hierarchial PLD’s

25

EC6601 VLSI Design Prof.B.Sathyabhama

 SYMMETRICAL ARRAYS
Logic
Block

I /O
Block

Horizontal Vertical routing

routing track track 26

EC6601 VLSI Design Prof.B.Sathyabhama

ROW BASED ARCHITECTURE

I /O BLOCK
Routing
Channels

I /O BLOCK
I /O BLOCK

Logic block rows

I /O BLOCK

27

EC6601 VLSI Design Prof.B.Sathyabhama

HIERARCHIAL PLD’S

I/O BLOCKS
I/O BLOCKS Logic Module

I/O BLOCKS
I/O BLOCKS Interconnects
28

EC6601 VLSI Design Prof.B.Sathyabhama

FPGA CLASSIFICATION
� FPGA is classified into three types such as
�Antifuse Programmed
�SRAM Programmed
�EEPROM Programmed

29

EC6601 VLSI Design Prof.B.Sathyabhama

ANTIFUSE BASED FPGA

30

EC6601 VLSI Design Prof.B.Sathyabhama

SRAM PROGRAMMED
SRAM CELL

31

EC6601 VLSI Design Prof.B.Sathyabhama

 EEPROM TRANSISTOR

32

EC6601 VLSI Design Prof.B.Sathyabhama

 ALTERA MAX SERIES

� LAB(Logic Array Block)

� Programmable AND array + fixed OR array +
programmable inversion
� Each LAB contains 16 macro cells.

33

EC6601 VLSI Design Prof.B.Sathyabhama

 MAX FAMILY MACRO CELL

34

EC6601 VLSI Design Prof.B.Sathyabhama

ARCHITECTURE OF MAX INTERCONNECT
7000 AND MAX 9000

35

EC6601 VLSI Design Prof.B.Sathyabhama

 INTERCONNECT ARCHITECTURE OF XILINX
XC4000

36

EC6601 VLSI Design Prof.B.Sathyabhama

PROGRAMMABLE INPUT OUTPUT BLOCK OF
XC4000

37

EC6601 VLSI Design Prof.B.Sathyabhama

 BLOCK DIAGRAM OF XC4000

38

EC6601 VLSI Design Prof.B.Sathyabhama

FPGA INTERCONNECT ROUTING PROCEDURES

� Global routing architecture

⚫ Hierarchical style
⚫ Island style
� Detailed routing architecture

39

EC6601 VLSI Design Prof.B.Sathyabhama

 ISLAND STYLE ROUTING
ARCHITECTURE

40

EC6601 VLSI Design Prof.B.Sathyabhama

ROUTING TRACKS

The routing tracks connected through a switch box can be

⚫ Bidirectional tracks
⚫ Unidirectional tracks (or) directional tracks

41

EC6601 VLSI Design Prof.B.Sathyabhama

HIERARCHICAL ROUTING ARCHITECTURE

� It is also termed as tree based architecture.

� The connection between logic blocks within same cluster
are made by wire segments at lowest level of hierarchy.
� The signal band width varies from bottom level and it is
widest at top level of hierarchy.

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EC6601 VLSI Design Prof.B.Sathyabhama

GLOBAL ROUTING
� Two main areas to global route
⮚ Inside the flexible blocks
⮚ Between the flexible blocks

Objectives of global routing

⮚ Minimize the total interconnect length
⮚ Maximize the probability that the detailed router can
complete the routing
⮚ Minimize the critical path delay
43

EC6601 VLSI Design Prof.B.Sathyabhama

GLOBAL ROUTING METHODS
� Two approaches in global routing
1.Sequential routing – handles the net one at a time.
2.Hierachical routing- handles all nets at a particular level at ones.
⚫Top down approach
⚫Bottom up approach

44

EC6601 VLSI Design Prof.B.Sathyabhama

ALGORITHMS FOR ROUTING
� Left edge Algorithm – to solve the restricted channel routing
problems.
� Lee – Maze running algorithm
� High tower algorithm.

45

EC6601 VLSI Design Prof.B.Sathyabhama

HIGH TOWER ALGORITHM
Steps of the algorithm
� Extend lines from both the source and target towards each
other

� When an extended line known as escape line meets an obstacle,

draw perpendicular line. This point is called the escape point.

� Escape line emerging from the source and target intersect to

form the path.
46

EC6601 VLSI Design Prof.B.Sathyabhama

� Multilevel routing
⚫ HVH(Metal M1&M3- Horizontal metal, M2-vertical)
⚫ VHV(Metal M1&M3- vertical metal, M2- Horizontal)
� Special routing
Routing that requires special attention for clock and power nets.

47

EC6601 VLSI Design Prof.B.Sathyabhama

� Clock routing
⚫ Array uses clock spine which eliminates the need for speed
routing.
⚫ The clock distribution grid is signed at the same time as the
gate array base to ensure minimum clock skew and minimum
clock latency.
• Power routing
Power bases should be sized according to its current carrying
capacity.
48

EC6601 VLSI Design Prof.B.Sathyabhama