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CHIP1
CHIP1
Connection in two paralleled serial chains Multiple independent paths with common
TMS and TCK signals
SGMII SerDes
/SGMII
FLEEP i/f EEPROM LOGIC STAT REGS LED STRECH
PCI
GIO
GHOST
Target i/f LAN_PORT
MNG-HOST TARGET LOGIC
MNG-LAN
CAR ARBEL
CLK_
XTX WRAP
DMA
CB HDR MAC_TX
TX
GHOST i/f DMA TX CB
CB MAC
PB
Q CORE
RX FILTER MAC_RX
DMA RX PHY
DMA
CB HDR
CB
RX MACPHY_
GLUE
FLEEP
SGMII SerDes
FLEEP i/f
/SGMII
EEPROM LOGIC STAT REGS LED STRECH
THERMAL
CLOCK_RESET_COMM IO RING GLUE (DFT,Jtag,BSCAN) PERIPHERY IO Buff ULT_WRAP CCM
asynchronous
lan_pwrgood
maximum of
asynchronous 5 clocks
Test-Logic-Reset with TMS
TRST_N
signal hold
TMS=1'b1
at 1'b1 The TAP state machine
19 JTAG course - Dolev Eyal
The TAP state machine
Run-Test/Idle
– The idle state of the TAP
controller.
– The contents of all test data
registers retain their
previous values.
– Self tests may run.
Shift-DR-Scan
– Temporary controller state.
Shift-IR-Scan
– Temporary controller state.
Test-Logic-reset
Run-Test/Idle
Select-DR-Scan
Select-IR-Scan
Capture-IR
Shift-IR
Exit1-IR
Pause-IR
Exit2-IR
Update-IR
Instruction scan
Update_ir
Tst_lgc_rst Actual Instruction Register
Cupture_ir
Shift_ir
Shift Register
Tst_lgc_rst
SGMII SerDes
/SGMII
FLEEP i/f EEPROM LOGIC STAT REGS LED STRECH
PCI
GIO
GHOST
Target i/f LAN_PORT
MNG-HOST TARGET LOGIC
MNG-LAN
CAR ARBEL
CLK_
XTX WRAP
DMA
CB HDR MAC_TX
TX
GHOST i/f DMA TX CB
CB MAC
PB
Q CORE
RX FILTER MAC_RX
TCK DMA
RX
DMA RX
CB HDR
CB
MACPHY_
PHY
TMS FLEEP
GLUE
SGMII SerDes
TDI
FLEEP i/f
/SGMII
EEPROM LOGIC STAT REGS LED STRECH
Chip_dft