KAUSHIKA TRAINING

INSTITUTE
GURUBHYO NAMAHA.
ASIC FLOW
Design name/ Block name VERILOG

Semicolon at every end of

line except endmodule

Logic Gate Level Representation of Code post

ASIC Synthesis

endmodule
MUX
MUX
DFF
DFF WITHOUT RESET PIN
 Synthesizable and Non Synthesizable RTL
• Logic synthesis is the process of converting a high-level description of
the design like RTL-HDL into an optimized gate-level representation,
given a standard cell library and certain design constraints
DFT- Design for Testablity
CONTROLLABILITY:
Design for Testability (DFT) is basically meant for providing a method
for testing each and every node in the design for structural and other
faults.
OBSERVABILITY:
By observability, we mean out ability to measure the state of a logic
signal. When we say that a node is observable, we mean that the value
at the node can be shifted out through scan shift patterns and can be
observed through output ports. 
Understanding Shift & Capture
DFT SHIFT AND CAPTURE
 Lintra and Spyglass
Logs:sgdft_drc.log:gives info about drc violations
 Clock_11: All clock sources must be testclock controlled during shift mode
 Async_07: Async set/reset should be inactive during shift
 Latch_08: all latches other than retiming latches must be transparent in capture mode

Reports:Summary.rpt,moresimple.rpt,stuck_at_coverage.rpt,scan_wra
pt.rpt,stuck_at_coverage_audit.rpt,ip_audit.rpt
SYNTHESIS COMMANDS