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Algebraic Methods For The Analysis and Synthesis of Logic Circuits
Algebraic Methods For The Analysis and Synthesis of Logic Circuits
Algebraic Methods For The Analysis and Synthesis of Logic Circuits
Chapter 2 1
Fundamentals of Boolean Algebra (1)
• Basic Postulates
• Postulate 1 (Definition): A Boolean algebra is a closed algebraic system
containing a set K of two or more elements and the two operators and +.
• Postulate 2 (Existence of 1 and 0 element):
(a) a + 0 = a (identity for +), (b) a 1 = a (identity for )
• Postulate 3 (Commutativity):
(a) a + b = b + a, (b) a b = b a
• Postulate 4 (Associativity):
(a) a + (b + c) = (a + b) + c (b) a (bc) = (ab) c
• Postulate 5 (Distributivity):
(a) a + (bc) = (a + b) (a + c) (b) a (b + c) = ab + ac
• Postulate 6 (Existence of complement):
(a) a(b)
a 1 aa 0
• Normally is omitted.
Chapter 2 2
Fundamentals of Boolean Algebra (2)
• Theorem 1 (Idempotency):
(a) a + a = a (b) aa = a
• Theorem 2 (Null element):
(a) a + 1 = 1 (b) a0 = 0
• Theorem 3 (Involution)
a a
• Properties of 0 and 1 elements (Table 2.1):
OR AND Complement
a+0=0 a0 = 0 0' = 1
a+1=1 a1 = a 1' = 0
Chapter 2 3
Fundamentals of Boolean Algebra (3)
• Theorem 4 (Absorption)
(a) a + ab = a (b) a(a + b) = a
• Examples:
– (X + Y) + (X + Y)Z = X + Y [T4(a)]
– AB'(AB' + B'C) = AB' [T4(b)]
• Theorem 5
(a) a + a'b = a + b (b) a(a' + b) = ab
• Examples:
– B + AB'C'D = B + AC'D [T5(a)]
– (X + Y)((X + Y)' + Z) = (X + Y)Z [T5(b)]
Chapter 2 4
Fundamentals of Boolean Algebra (4)
• Theorem 6
(a) ab + ab' = a (b) (a + b)(a + b') = a
• Examples:
– ABC + AB'C = AC [T6(a)]
– (W' + X' + Y' + Z')(W' + X' + Y' + Z)(W' + X' + Y + Z')(W' + X' + Y + Z)
= (W' + X' + Y')(W' + X' + Y + Z')(W' + X' + Y + Z) [T6(b)]
= (W' + X' + Y')(W' + X' + Y) [T6(b)]
= (W' + X') [T6(b)]
Chapter 2 5
Fundamentals of Boolean Algebra (5)
• Theorem 7
(a) ab + ab'c = ab + ac (b) (a + b)(a + b' + c) = (a + b)(a + c)
• Examples:
– wy' + wx'y + wxyz + wxz' = wy' + wx'y + wxy + wxz' [T7(a)]
= wy' + wy + wxz' [T7(a)]
= w + wxz' [T7(a)]
=w [T7(a)]
– (x'y' + z)(w + x'y' + z') = (x'y' + z)(w + x'y') [T7(b)]
Chapter 2 6
Fundamentals of Boolean Algebra (6)
• Examples:
– (a + bc)' = (a + (bc))'
= a'(bc)' [T8(a)]
= a'(b' + c') [T8(b)]
= a'b' + a'c' [P5(b)]
– Note: (a + bc)' a'b' + c'
Chapter 2 7
Fundamentals of Boolean Algebra (7)
Chapter 2 8
Fundamentals of Boolean Algebra (8)
• Theorem 9 (Consensus)
(a) ab + a'c + bc = ab + a'c (b) (a + b)(a' + c)(b + c) = (a + b)(a' + c)
• Examples:
– AB + A'CD + BCD = AB + A'CD [T9(a)]
– (a + b')(a' + c)(b' + c) = (a + b')(a' + c) [T9(b)]
– ABC + A'D + B'D + CD = ABC + (A' + B')D + CD [P5(b)]
= ABC + (AB)'D + CD [T8(b)]
= ABC + (AB)'D [T9(a)]
= ABC + (A' + B')D [T8(b)]
= ABC + A'D + B'D [P5(b)]
Chapter 2 9
Switching Functions
Chapter 2 11
Truth Tables (2)
Chapter 2 12
Algebraic Forms of Switching Functions (1)
Chapter 2 13
Algebraic Forms of Switching Functions (2)
• A minterm is a product term in which all the variables appear exactly once
either complemented or uncomplemented.
• Canonical Sum of Products (canonical SOP):
– Represented as a sum of minterms only.
– Example: f1(A,B,C) = A'BC' + ABC' + A'BC + ABC (2.1)
• Minterms of three variables:
Minterm Minterm Code Minterm Number
A'B'C' 000 m0
A'B'C 001 m1
A'BC' 010 m2
A'BC 011 m3
AB'C' 100 m4
AB'C 101 m5
ABC' 110 m6
ABC 111 m7
Chapter 2 14
Algebraic Forms of Switching Functions (3)
• m
i 0
i 1 (2.6)
• AB + (AB)' = 1 and AB + A' + B' = 1, but AB + A'B' 1.
Chapter 2 16
Algebraic Forms of Switching Functions (5)
• A maxterm is a sum term in which all the variables appear exactly once either
complemented or uncomplemented.
• Canonical Product of Sums (canonical POS):
– Represented as a product of maxterms only.
– Example: f2(A,B,C) = (A+B+C)(A+B+C')(A'+B+C)(A'+B+C') (2.7)
• Maxterms of three variables:
Maxterm Maxterm Code Maxterm Number
A+B+C 000 M0
A+B+C' 001 M1
A+B'+C 010 M2
A+B'+C' 011 M3
A'+B+C 100 M4
A'+B+C' 101 M5
A'+B'+C 110 M6
A'+B'+C' 111 M7
Chapter 2 17
Algebraic Forms of Switching Functions (6)
Chapter 2 18
Algebraic Forms of Switching Functions (7)
• Truth tables of f1(A,B,C) of Eq. (2.3) and f2(A,B,C) of Eq. (2.7) are identical.
• Hence, f1(A,B,C) = m (2,3,6,7)
= f2(A,B,C)
= M(0,1,4,5) (2.10)
• Example: Given f(A,B,C) = ( A+B+C')(A+B'+C')(A'+B+C')(A'+B'+C'),
construct the truth table and express in both maxterm and minterm form.
– f(A,B,C) = M1M3M5M7 = M(1,3,5,7) = m (0,2,4,6)
Row No. Inputs Outputs
(i) ABC f(A,B,C)= M(1,3,5,7) = m(0,2,4,6)
0 000 1 m0
1 001 0 M1
2 010 1 m2
3 011 0 M3
4 100 1 m4
5 101 0 M5
6 110 1 m6
Chapter 2 7 111 0 M7 19
Algebraic Forms of Switching Functions (8)
Chapter 2 20
Algebraic Forms of Switching Functions (9)
Chapter 2 21
Algebraic Forms of Switching Functions (10)
Chapter 2 22
Derivation of Canonical Forms (1)
Chapter 2 23
Derivation of Canonical Forms (2)
• Example: f(A,B,C) has minterms m0, m3, and m7 and don't-cares d4 and d5.
– Minterm list is: f(A,B,C) = m(0,3,7) + d(4,5)
– Maxterm list is: f(A,B,C) = M(1,2,6)·D(4,5)
– f '(A,B,C) = m(1,2,6) + d(4,5) = M(0,3,7)·D(4,5)
– f (A,B,C)= A'B'C' + A'BC + ABC + d(AB'C' + AB'C)
= B'C' + BC (use d4 and omit d5)
Chapter 2 25
Electronic Logic Gates (1)
Chapter 2 26
Electronic Logic Gates (2)
a a &
AND f ( a , b ) = ab AND f ( a , b ) = ab
b b
³
a a 1
OR f(a , b )= a + b OR f(a , b )= a + b
b b
a 1
NOT a f(a )= a NOT f(a )= a
b
a a &
NAND f ( a , b ) = ab NAND f ( a , b ) = ab
b b
³
a a 1
NOR f(a , b )= a + b NOR f(a , b )= a + b
b b
a a
EXCLUSIVE
OR
f(a , b )= a b EXCLUSIVE
OR
=1 f(a , b )= a b
b b
Chapter 2 27
Electronic Logic Gates (3)
V cc 4B 4A 4Y 3B 3A 3Y V cc 4Y 4B 4A 3Y 3B 3A
14 13 12 11 10 9 8 14 13 12 11 10 9 8
1 2 3 4 5 6 7 1 2 3 4 5 6 7
1A 1B 1Y 2A 2B 2Y GND 1Y 1A 1B 2Y 2A 2B GND
7400: Y = AB 7402: Y = A + B
Quadruple two-input NAND gates Quadruple two-input NOR gates
V cc 6A 6Y 5A 5Y 4A 4Y V cc 4B 4A 4Y 3B 3A 3Y
14 13 12 11 10 9 8 14 13 12 11 10 9 8
1 2 3 4 5 6 7 1 2 3 4 5 6 7
1A 1Y 2A 2Y 3A 3Y GND 1A 1B 1Y 2A 2B 2Y GND
7404: Y = A 7408: Y = AB
Hex inverters Quadruple two-input AND gates
Chapter 2 28
Electronic Logic Gates (4)
V cc 1C 1Y 3C 3B 3A 3Y V cc 2D 2C NC 2B 2A 2Y
14 13 12 11 10 9 8 14 13 12 11 10 9 8
1 2 3 4 5 6 7 1 2 3 4 5 6 7
1A 1B 2A 2B 2C 2Y GND 1A 1B NC 1C 1D 1Y GND
7410: Y = ABC 7420: Y = ABCD
Triple three-input NAND gates Dual four-input NAND gates
Chapter 2 29
Electronic Logic Gates (5)
V cc NC H G NC NC Y V cc 4B 4A 4Y 3B 3A 3Y
14 13 12 11 10 9 8 14 13 12 11 10 9 8
1 2 3 4 5 6 7 1 2 3 4 5 6 7
A B C D E F GND 1A 1B 1Y 2A 2B 2Y GND
7430: Y = ABCDEFGH 7432: Y = A + B
8-input NAND gate Quadruple two-input OR gates
V cc 4B 4A 4Y 3B 3A 3Y
14 13 12 11 10 9 8
1 2 3 4 5 6 7
1A 1B 1Y 2A 2B 2Y GND
7486: Y = A Å B
Quadruple two-input exclusive-OR gates
Chapter 2 30
Basic Functional Components (1)
• AND
A
a b f AND ( a , b ) = ab A B Y Y
B
0 0 0 L L L (c)
0 1 0 L H L
1 0 0 H L L A & Y
1 1 1 H H H B
(a) (b) (d)
Chapter 2 31
Basic Functional Components (2)
• OR
A
a b f OR ( a , b ) = a + b A B Y Y
B
0 0 0 L L L (c)
0 1 1 L H H
1 0 1 H L H A Y
1 1 1 H H H B
(a) (b) (d)
Chapter 2 32
Basic Functional Components (3)
Chapter 2 33
Basic Functional Components (4)
• NOT
A Y
(c)
a f NOT (a )= a A Y
0 1 L H A 1 Y
1 0 H L
(a) (b) (d)
Chapter 2 34
Basic Functional Components (5)
Chapter 2 35
Basic Functional Components (6)
A B Y a
y = a + b
1 1 1 b
1 0 1 A
Y (c)
0 1 1 B
0 0 0 a
(a) (b) y = ab
b
(d)
– (a) AND gate truth table (L = 1, H = 0)
– (b) Alternate AND gate symbol (in negative logic)
– (c) Preferred usage
– (d) Improper usage
– y = a·b = (2.14)
a b a b fOR (a , b )
– (2.15)
y (a ) (b ) a b fOR (a, b)
Chapter 2 36
Basic Functional Components (7)
A B Y a
y = ab
1 1 1 b
1 0 0 A
Y (c)
0 1 0 B
0 0 0 a
(a) (b) y = a + b
b
(d)
Chapter 2 38
Basic Functional Components (9)
Smoke
detectors
Sprinkler
D1 D 1 +D 2
G1
D2
SPK
Telephone
D 1 D 2 dialer
G2
DIAL
Chapter 2 39
Basic Functional Components (10)
• NAND
a b f NAND ( a , b ) = ab A B Y
0 0 1 L L H
0 1 1 L H H
1 0 1 H L H
1 1 0 H H L
(a) (b)
A A A &
Y Y Y
B B B
Chapter 2 40
Basic Functional Components (10)
a a
y y
b b
a a
y y
b b
(a) (b)
• Additional properties of NAND gate:
• AND, OR, and NOT gates constructed exclusively from NAND gates
a ab a f ( a , a ) =a a = a
f ( a , b ) = ab = ab
b
a a
f ( a , b )= a + b = a + b
b
b
OR gate
Chapter 2 42
Basic Functional Components (12)
• NOR
a b f NOR ( a , b ) = a + b A B Y
0 0 1 L L H
0 1 0 L H L
1 0 0 H L L
1 1 0 H H L
(a) (b)
A A A ³1
Y Y Y
B B B
a a
y y
b b
a a
• Additional properties y y
b of NAND gate: b
(a) (b)
Chapter 2 44
Basic Functional Components (14)
• AND, OR, and NOT gates constructed exclusively from NOR gates.
a a + b
f(a , b )= a + b a f(a , a )= a + a = a
b
a a
f ( a , b ) = ab = ab
b
b
AND gate
Chapter 2 45
Basic Functional Components (15)
• Exclusive-OR (XOR)
– fXOR(a, b) = a b = (2.24)
a b ab
ab fXOR(a, b) = a b AB Y
00 0 LL L
01 1 LH H
10 1 HL H
11 0 HH L
(a) XOR logic function (b) Electronic XOR gate
A A
Y =1 Y
B(c) Standard symbol B
(d) IEEE block symbol
Chapter 2 46
Basic Functional Components (16)
• POS of XOR
a b a b ab
[P2(a), P6(b)]
a a a b ab bb
[P5(b)]
a ( a b) b ( a b)
[P5(b)]
(a b )(a b)
• Some other useful relationships
– a a = 0 (2.25)
– a = 1 (2.26)
a
– a 0 = a (2.27)
– a1= (2.28)
– (2.29)
a
a b ab
– ab=ba (2.30)
– a (b c) = (a b) c (2.31)
Chapter 2 47
Basic Functional Components (17)
• Output of XOR gate is asserted when the mathematical sum of inputs is one:
Chapter 2 48
Basic Functional Components (18)
• Exclusive-NOR (XNOR)
– fXNOR(a, b) = a b (2.32)
ab
A
a b f XNOR ( a , b ) = a b A B Y Y
B
0 0 1 L L H (c)
0 1 0 L H L
1 0 0 H L L A =1
1 1 1 H H H Y
– (a) XNOR logic function B
(a) (b)
– (b) Electronic XNOR gate (d)
– (c) Standard symbol
– (d) IEEE block symbol
Chapter 2 49
Basic Functional Components (19)
• ab = a b
Chapter 2 50
Analysis of Combinational Circuits (1)
• Analysis is used
– To determine the behavior of the circuit
– To verify the correctness of the circuit
– To assist in converting the circuit to a different form.
Chapter 2 51
Analysis of Combinational Circuits (2)
• Example 2.33: Find a simplified switching expressions and logic network for
the following logic circuit (Fig. 2.21a).
a P1
b
P4
a
c P2 f (a, b , c)
b P3
c
(a)
Chapter 2 52
Analysis of Combinational Circuits (3)
Chapter 2 53
Analysis of Combinational Circuits (4)
• Example 2.34: Find a simplified switching expressions and logic network for
the following logic circuit (Fig. 2.22).
a a b
b
(a b )( b c)
b
c b c
f (a , b , c )
a a + b
b
a a + b + a + c
c a + c
Given circuit
Chapter 2 54
Analysis of Combinational Circuits (5)
Chapter 2 55
Analysis of Combinational Circuits (6)
• Truth Table Method: Derive the truth table one gate at a time.
Chapter 2 56
Analysis of Combinational Circuits (7)
Chapter 2 57
Analysis of Combinational Circuits (8)
A
A
B Y = fa (A , B , C ) B
C
Inputs
Outputs
Z = fb (A , B , C ) Y = fa (A , B , C )
Z = fb (A , B , C )
C
t0 t1 t2 t3 t4 t5 t6 t7
(a)
(b)
Inputs Outputs
Time ABC fa(A , B , C ) fb(A , B , C )
t0 000 0 0
t1 001 1 1
t2 010 1 0
t3 011 0 1
t4 100 0 0
t5 101 0 1
t6 110 1 1
t7 111 1 0
Chapter 2 (c) 58
Analysis of Combinational Circuits (9)
• Propagation Delay
– Physical characteristics of a logic circuit to be considered:
• Propagation delays
• Gate fan-in and fan-out restrictions
• Power consumption
• Size and weight
– Propagation delay: The delay between the time of an input change and the
corresponding output change.
– Typical two propagation delay parameters:
• tPLH = propagation delay time, low-to-high-level output
• tPHL = propagation delay time, high-to-low-level output
– Approximation:
• t PLH t PHL
t PD
2
Chapter 2 59
Analysis of Combinational Circuits (10)
b
a
c
b c
a a
b b
c c
t PD t PD t PLH t PHL
(c) t PD = t PLH = t PHL (d) t PLH < t PHL
Chapter 2 60
Analysis of Combinational Circuits (11)
• Power dissipation and propagation delays for several logic families (Table 2.7)
Chapter 2 61
Analysis of Combinational Circuits (12)
tPLH tPHL
Chip Function Typical Maximum Typical Maximum
74LS04 NOT 9 15 10 15
74LS00 NAND 9 15 10 15
74LS02 NOR 10 15 10 15
74LS08 AND 8 15 10 20
22
74LS32 OR 14 22 14 22
Chapter 2 62
Analysis of Combinational Circuits (13)
• Example 2.36: Given a circuit diagram and the timing diagram, find the truth
table and minimum switching expression.
D
C F
A ABC f (A , B , C )
Y = f (A , B , C ) 000 0
001 1
E 010 0
B G 011 0
100 1
101 1
110 1
A
111 0
B
D f ( A, B, C )
E
m(1,4,5,6)
F
G
A B C AB C AB C ABC
f (A , B , C ) AC B C
t0 t1 t3 t4 t5 t6 t7
t1 +2 t2 t2 +2 t4 +3 t7 +3
t4 +2 t7 +2
t1 +1 t2 +1 t4 +1 t7 +1
Chapter 2 63
Synthesis of Combinational Logic Circuits (1)
– [T3]
f ( p, q, r[T8(a)]
, s ) pr qrs ps
pr qrs ps
where x1 x2 x3 and
x1 pr , x2 qrs, x3 ps
Chapter 2 64
Synthesis of Combinational Logic Circuits (2)
– f ( A, B, C , D) ( A B C )( B C D)( A D) [T3]
A BC BC D A D [T8(b)]
y1 y2 y3
where y1 A B C , y2 B C D, and y3 A D
Chapter 2 65
Synthesis of Combinational Logic Circuits (3)
• Two-level Circuits
– Input signals pass through two levels of gates before reaching the output.
p p
x1 x1
r r
q x2 fd (p , q , r, s) q x2 fd (p , q , r, s)
r r
s s
p x3 p x3
s s
Level 2 Level 1 Level 3 Level 2 Level 1
(a) Two-level network (b) Three-level network
Chapter 2 66
Synthesis of Combinational Logic Circuits (4)
• Circuits with more than two levels are often needed due to fan-in constraints.
a
b
c f = abcde
d
e
(a) A single five-input AND gate
a
a b
b
c
c
d
d f = abcde
f = abcde
e e
(b) Three-level network of two-input gates (c) Four-level network of two-input gates.
Chapter 2 67
Synthesis of Combinational Logic Circuits (5)
Y f (X , Y , Z )
Z
X
Z
(a) NAND implementation
Chapter 2 68
Synthesis of Combinational Logic Circuits (6)
• AND-OR-invert Circuits
– A set of AND gates followed by a NOR gate.
– Used to readily realize two-level SOP circuits.
– 7454 circuit: F AB CD EF GH
Make no external
connection
V cc B H G Y
14 13 12 11 10 9 8 A
Y1
B
C
Y2
D
Y
Output
E
Y3
F
G
Y4
H
1 2 3 4 5 6 7
A C D E F NC GND Enable lines
(a) 7454 circuit package (top view) (b) 7454 used as a 4-to-1 multiplexer
Chapter 2 69
Synthesis of Combinational Logic Circuits (7)
• Factoring
– A technique to obtain higher-level forms of switching functions.
– Higher-level forms:
• May need less hardware
• May be used when there are fan-in constraints
• More difficult to design
• Slower
• Example 2.39:
f ( A, B, C , D) AB AD AC A( B D C ) A( BCD)
A
B A f (A , B , C , D )
A f (A , B , C , D )
D B
C
A D
C
Chapter 2 (a) Original form (b) After factoring 70
Synthesis of Combinational Logic Circuits (8)
• Example 2.40: f (a,b,c,d) = m(8,13) with only two-input AND and OR gates.
– Write the canonical SOP form:
f (a,b,c,d) = m(8,13) = ab c d abc d (2.34)
Two four-input AND gates and one two-input OR gate are needed.
– Apply factoring:
f (a, b, c, d ) ab c d abc d (ac )(bd b d )
(2.35)
b
d
f =( a , b , c , d )
c
a
Chapter 2 71
Synthesis of Combinational Logic Circuits (9)
• Example 2.41: A burglar alarm with four control switches, each of which
produces logic 1 when:
Switch A: Secret switch is closed
Switch B: Safe is in its normal position in the closet
Switch C: Clock is between 1000 and 1400 hours
Switch D: Closet door is closed.
Write the equations of the control logic that produces logic 1 when
the safe is moved AND the secret switch is closed,
OR
the closet is opened after banking hours,
OR
the closet is opened with the control switch open.
f ( A, B, C , D) AB C D A D
Chapter 2 72
Synthesis of Combinational Logic Circuits (10)
C
D
f (A , B , C , D )
Chapter 2 73
Synthesis of Combinational Logic Circuits (11)
• Example 2.43: Logic equations for a circuit that adds two 2-bit binary
numbers (A1A0)2 and (B1B0)2, and produces sum bits (S1S0)2 and carry bit C1;
A1 A0
+ B1 B0
C1S1S0
Chapter 2 74
Synthesis of Combinational Logic Circuits (12)
Chapter 2 75
Synthesis of Combinational Logic Circuits (13)
• Reduced equations:
S0 = A0 B0 A0 B0
S1 = A1 A0 B1 A1B1B0 A1 A0 B1B0
A1 A0 B1B0 A1B1B0 A1 A0 B1
C1 = A0 B1B0 A1 A0 B0 A1B1
Chapter 2 76
Computer-aided Design (1)
• Design Cycle
Concept
Modeling
and
design capture
Synthesis
Logic
simulation
Analysis
Fail Results
?
Pass
Implementation
Realization
Physical
design
Testing
Test
Finished circuit
Chapter 2 77
Computer-aided Design (2)
Level Abstraction
Behavioral Algorithms to be realized
Register Structure of modules
Transfer Data flow among modules and control algorithm
Gate Structure of primitive logic gates
Transistor Structure of transistors and low-level components
Layout Geometric patterns of materials for IC layout
Chapter 2 78
Computer-aided Design (3)
Chapter 2 79
Computer-aided Design (4)
a b c in
a b c in c out s
0 0 0 0 0
0 0 1 0 1 s= a b c
Full_adder 0 1 0 0 1 in
0 1 1 1 0 c out = ab + ac in
+ bc in
1 0 0 0 1
1 0 1 1 0 (c)
1 1 0 1 0
c out s 1 1 1 1 1
(a) (b)
Chapter 2 80
Computer-aided Design (5)
• Structural model
– Interconnection of components.
– Behavior is deduced from the behavioral models of individual
components and their interconnection.
– Represented by:
• Logic or schematic diagram
• Netlist (textual representation of schematic diagram)
• HDL description of circuit structures.
Chapter 2 81
Computer-aided Design (6)
(a) (b)
– In a netlist, each circuit element is defined as follows:
gate_name, gate_type, output, input1, input2, …, inputN
– VHDL structural model of a full-adder circuit: Figure 2.40.
Chapter 2 82
Computer-aided Design (7)
• Mixed-mode model
– Contains both behavioral and structural components.
– Mixed-mode model of the full-adder circuit: (a) full-adder block diagram,
(b) circuit for sum function, (c) truth table for carry function.
a b c in c out
a
b Sum s 0 0 0 0
c in module 0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
Carry 1 0 1 1
c out 1 1 0 1
module
1 1 1 1
(a) (c)
a
b s
c in
(b)
Chapter 2 83
Computer-aided Design (8)
Schematic Netlist
Logic
equations Design
Component
library optimization
Constraints Minimize
Schematic
Optimized
Back logic Netlist
annotation equations generation
Map design
Component onto circuit
library elements
Circuit
netlist
Chapter 2 84
Computer-aided Design (9)
• Capture tools
– Each circuit model in the design process must be captured in a format that
can be stored and processed by a digital computer.
– Schematic capture: an interactive graphics tool with which a designer
draws a logic diagram.
Chapter 2 85
Computer-aided Design (10)
(a) (b)
(c) (d)
Chapter 2 86
Computer-aided Design (11)
• Logic Simulation
– Three primary purposes:
1. Logic verification: only logical correctness is checked.
2. Performance analysis: propagation delays and potential timing
problems are analyzed.
3. Test development (fault simulation): helps develop optimal test set.
– Simulation environment
Design
Netlist Test
vectors
Component Simulator
models
Logic Timing
verification analysis
data data
Chapter 2 87
Computer-aided Design (12)
• Event-Driven Simulation
– Event: a change in the value of a signal at a given time.
– Event-driven simulation example for an AND gate:
b
a c
c
b
T0 T1 T1 + t T2
(a) (b)
Chapter 2 89
Computer-aided Design (14)
Chapter 2 90
Computer-aided Design (15)
Time a b c in s Time a bc in n1 n2 n3 n4 s
a n1
00 0 0 X XX X X
0 0 0 0 X 10 0 0 1 1X 1X
b
n2
3 0 0 0 1 20 0 0 1 10 1X
30 0 0 1 10 11
n3
s 5 0 1 0 1 50 1 0 1 10 11
c in 10 1 1 0 1 10 1 1 0 1 10 11
12 1 1 0 1 11 11
n4 13 1 1 0 0 13 1 1 0 1 11 10
15 1 0 0 1 11 10
15 1 0 0 0 17 1 0 0 1 01 10
18 1 0 0 1 18 1 0 0 1 01 11
Chapter 2 91
Computer-aided Design (16)
d
e
f
a e g
b g
d
c f Time t t t
t1 t2 t3 t4
(a) (b)
Chapter 2 92
Computer-aided Design (17)
AND 0 1 X OR 0 1 X NOT 0
0 0 0 0 0 0 1 X 0 1
1 0 1 X 1 1 1 1 1 0
X 0 X X X X 1 X X X
Chapter 2 93
Computer-aided Design (18)
V CC
F0 I1 F1
Ux
I1 I2
F0 R1 F1
F0
F0
(b)
I2
F1
F0
Chapter 2 94
Computer-aided Design (19)
a c*
t c
b
Ideal Time
gate delay
Chapter 2 95
Computer-aided Design (20)
• Unit/Nominal Delay
– Unit delay: assign to each gate in a circuit the same unit delay.
– Nominal delay: delays are determined separately for each type of gate
(e.g., on time unit for NOR and two time units for XOR).
t t
Chapter 2 96
Computer-aided Design (21)
• Rise/Fall Delay
– Different delays for 0 to 1 transition and 1 to 0 transition.
– tPLH (rise time): propagation delay from low to high.
– tPHL (fall time): propagation delay from high to low.
t PLH t PHL
(rise time) (fall time)
Chapter 2 97
Computer-aided Design (22)
c
t min
t max
Chapter 2 98
Computer-aided Design (23)
h
15
10 12 14 16 20 25
Chapter 2 99
Computer-aided Design (24)
• Inertial Delay
– An input value must persist for some minimum duration of time to
provide the output with the needed inertia to change.
– The minimum duration is called inertial delay.
– Effect of inertial delay:
a a
b b
c c
(a) Transport delay model (b) Inertial delay model
t a*
a
c* t c
b t
b*
Inertial Ideal Transport
delay gate delay
Chapter 2 100