Switching delay in BiCMOS

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Applications
Switching Delay in BiCMOS
• BiCMOS has large current driving capability.
• It is used for driving large capacitive loads.
• It can pull up the output voltage in about one fourth of the time
required for the CMOS inverter to pull up.
Switching Delay in BiCMOS
• Speed advantage is seen only for large capacitive loads.
• For small capacitive loads conventional CMOS is better.
• For small capacitive loads parasitic capacitances will influence.
Switching Delay in BiCMOS

BiCMOS during 1-0 condition

Switching Delay in BiCMOS
• The three time segments are defined according to the operating
modes of the transistors, as follows:
• During t1, the base-emitter voltage of Q1 increases from its initial
value to VBEturnon The bipolar transistor is in cut-off during this time
segment, and the pMOS transistor operates in the saturation region.
• During t2, the bipolar transistor starts conducting a non-zero current
in the forward active mode, and the pMOS transistor MP operates in
saturation.
• During t3, the pMOS operates in the linear region, and the bipolar
transistor continues to operate in the forward active mode.
Switching Delay in BiCMOS

Transient behavior of the BiCMOS inverter circuit.

Switching Delay in BiCMOS
• The differential equation describing the base-emitter voltage variation
of the bipolar transistor during t1,
Switching Delay in BiCMOS
• At the beginning of the time segment t2, the bipolar transistor Q 1
enters the forward active mode while the pMOS is operating in
saturation. The combined output capacitance Cload begins to charge
up due to the emitter current.
• The differential equations describing the time dependence of the
output and the base voltages are given in the following.,
Switching Delay in BiCMOS
• Note that high-level injection phenomena were found to be dominant
in bipolar transistors during the time segments t2 and t3.
• The dependence of the current gain factor upon the collector current
under high-level injection conditions is described by the Gummel-
Poon model as
Switching Delay in BiCMOS
• where Ik is called the knee current. Hence, the relationship between
the forward transit time and the collector current can be described by
Switching Delay in BiCMOS

BiCMOS during 0-1 condition

Applications:

BiCMOS NOR gate

BiCMOS NAND gate
• Here, the base of the bipolar pull-up transistor Q1 is being driven by
two series-connected pMOS transistors. Therefore, the pull-up device
can be turned on only if both of the inputs are logic-low.
• The base of the bipolar pull-down transistor Q2 is driven by two
parallel-connected nMOS transistors. Therefore, the pull-down device
can be turned on if either one or both of the inputs are logic-high.
BiCMOS NAND gate

BiCMOS NAND gate

Complex logic gate

Complex logic gate

CMOS Logic gate
• In this case, the base of the bipolar pull-up transistor Q I is being
driven by two parallel-connected pMOS transistors. Hence, the pull-
up device is turned on when either one or both of the inputs are
logic-low.
• The bipolar pull-down transistor Q2, on the other hand, is driven by
two series-connected nMOS transistors between the output node and
the base. Therefore, the pull-down device can be turned on only if
both of the inputs are logic-high.
BiCMOS column sense amplifier for high-speed memory array

BiCMOS column sense amplifier for high-speed memory array

BiCMOS column sense amplifier for high-speed memory array

• The circuit diagram of a typical column pair in a memory array with

the attached BiCMOS sense amplifier is shown in Fig.
• During the data read cycle, the bit-line differential voltage appears
between the respective base terminals of the bipolar differential pair.
Collector current flows in the bipolar device that has the higher base
current.
• Each bipolar device in the differential pair arrangement has its
collector terminal connected to one of the local data lines.
BiCMOS column sense amplifier for high-speed memory array

• Note that although each column pair in the memory array has its own
differential-pair amplifier, current can flow only in the sense amplifier
of the selected column.
• The current source of the bipolar differential pair is provided by an
nMOS device, which is controlled by the column select signal. Also,
the column pull-up operation is usually provided by bipolar transistors
in this BiCMOS memory array.