Sequential Circuits

In a combinational circuit, the values of the outputs are

determined only by the present values of its inputs.

In a sequential circuit, the values of the outputs

depend on the past behavior of the circuit, as well as
the present values of its inputs. Therefore, a sequential
logic circuit consists of combinational
Logic circuit and memory elements.

The most important memory element in a sequential

circuit is Flip flop. F/F circuit can be constructed from
either two NAND gates or two NOR gates.
Sequential circuits can be:
•Synchronous – where flip-flops are used to implement the
states, and a clock signal is used to control the operation. In
synchronous counter, every flip-flop is triggered
simultaneously which avoids accumulation of delay and
possible glitch.

•Asynchronous – In asynchronous counter, clocking of

consecutive flip-flops are through rippling and in different
point of time. Here

Synchronization is achieved by timing device called a system

clock. Which generate periodic train of clock pulses.
 The general form of a synchronous sequential circuit.

W Combinational Combinational
Flip-flops Z
circuit Q circuit

Clock

If the outputs depend only on the present state of the circuit inputs, the
circuit is said to be of Moore type

If the outputs depend on both the present state and the present values of the
inputs, the circuit is said to be of Mealy type.
 Y1 y1
w
Combinational Combinational z
circuit circuit

Y2 y2

Clock

The present state variables, y1 and y2, determine the present state of the
circuit.
The next state variables, Y1 and Y2, determine the state into which the circuit
will go after the next active edge of the clock signal.
 Basic Flip flop circuit
Bistable Circuit

• A bistable circuit has two Feedb

stable states. ack
• Its value changes only by
external trigger.
• It can store one bit of
information
 SR Latch
S R Qn Qn+1
(PS) (NS)
0 0 0 0 Latches to
0 0 1 1 prior state
0 1 0 0
0 1 1 0 State 0
S R V2 V3 1 0 0 1
1 1 0 0 1 0 1 1 State 1

If SR = 00 follows SR = 1 1 0 N.A.
Undefined
11, then there is a 1 1 1 N.A. State
race between two
gates and depending N.A.: Not
on who responds allowed
faster, V2V3 settles at
one of 01 or 10.
 SR Latch
S R Qn Qn+1
(PS) (NS)
0 0 0 0 Latches to
0 0 1 1 prior state
0 1 0 0
0 State
0 1 1 0
S R V2 V3 1 0 0 1
1 1 0 0 1 0 1 1 1 State

If SR = 00 follows SR = 1 1 0 N.A. Undefined

11, then there is a 1 1 1 N.A. State
race between two
gates and depending N.A.: Not
on who responds allowed
faster, V2V3 settles at
one of 01 or 10.
 Use K-map for Qn+1 and solve

Qn+1 = S + R’Qn

The characteristic equation is derived from the k-map. This

equation specifies the value of the next state as a function
of the present state and the output. This equation is used in
the design of sequential circuits to derive an excitation
table and obtain the excitation and output functions.
IC 74279

1 2

3 4

Truth Table of 2 Truth Table of 1

and 3 and 4
Gated Latch usually, Latch with clock / enable
input is referred as Flip-Flop.
Clocked SR Flip-Flop
Usually, Latch with clock / enable input is
referred as Flip-Flop.

When C is at HIGH level, state can

change according to SR input.
Level triggering is used
SR Latch Characteristic Table

S R Qn Qn+1
Excitation Table S-R Flip (PS) (NS)
Flop 0 0 0 0 Latches to
0 0 1 1 prior state
PS NS S R
0 0 0 X 0 1 0 0
0 State
0 1 1 0 0 1 1 0
1 0 0 1 1 0 0 1
1 0 1 1 1 State
1 1 X 0
1 1 0 N.A. Undefined
1 1 1 N.A. State
N.A.: Not
allowed
 Given: PS NS S R
PS=A, B, C, 0 0 0 X
NS= B,C,A
0 1 1 0
1 0 0 1
1 1 X 0

PS NS FF Inputs
Q1 Q0 Q1+ Q0+ S1 R1 S0 R0
0 0 0 1 0 X 1 0
0 1 1 0 1 0 0 1
1 0 0 0 0 1 0 X
1 1 X X X X X X
 Q0\Q1 0 1
0 1 0
1 0 X

S0=Q0’Q1’
R0= Q1
Q0\Q1 0 1 S1= Q1
0 0 1 R1= Q1’

1 x x

Q0\Q1 0 1
Q0\Q1 0 1
0 0 1
0 X 0
1 0 X
1 1 X
 Design a synchronous circuit which count following
sequence
0, 2, 4,6,7,0
L
A Analysis:
B GooGgg
S Three state & three flip flops are required
E
S PS= 000---010---100---110---111---000
S
I NS= 010—100---110---111---000
O
N Find FF Inputs?
S0,R0 S1, R1 S2, R2

Draw Excitation Table?

Use K-Map- so,ro,s1,r1,s2,r2
Draw switching circuit using IC74279
Timing diagram for the circuit.
 Sequences of input and output signals

Clockcycle: t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10
w: 0 1 0 1 1 0 1 1 1 0 1
z: 0 0 0 0 0 1 0 0 1 1 0
Present Next state Output
state w = 0 w = 1 z

A A B 0
B A C 0
C A C 1

State table for the sequential circuit

 Next state
Present
w = 0 w = 1 Output
state
Y Y Y
2 1 2 1 z
y2y1 Y
A

B 00 00 01 0
01 00 10 0
C 10 00 10 1
11 dd dd d

Figure 6.6. State-assigned table for the sequential circuit in Figure

6.4.
 yy
21
Ignoring don't cares Using don't cares
w 00 01 11 10

0 0 0 d 0
Y = wy 1 y 2 Y = wy 1 y 2
1 1
1 1 0 d 0

yy
21
w
00 01 11 10

0 0 0 d 0

1 0 1 d 1 Y = wy y 2 + wy 1 y Y = wy + wy
2 1 2 2 1 2

= w(y +y )
1 2

y
1
y 0 1
2

0 0 0

1 1 d
z=y1y
2 z=y
2
Figure 6.7. Derivation of logic expressions for the sequential circuit in Figure 6.6.
Final implementation of the sequential circuit.
 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10
1
Clock
0

1
w
0

1
y1
0

1
y2
0

1
z
0

Timing diagram for the circuit.

 Reset

w=1
w=0 Az=0 Bz=0
w=0

w=0 w=1

Cz=1

w=1

State diagram of a simple sequential

circuit.
 Design steps:
1. Obtain the specification of the desired circuit.
1. Derive a state diagram.
1. Derive the corresponding state table.
1. Reduce the number of states if possible.
1. Decide on the number of state variables.
1. Choose the type of flip-flops to be used.
2. Derive the logic expressions needed to
implement the circuit.
Figure 6.10. System for Example 6.1.
 w=0

A  No transfer
Reset

w=1

B  R2out =

1 R3in = 1
w =0
w =1 w =0
C  R1out = 1 R2
win = 1

w =0
w =1
D  R 3out = 1 R 1in = 1 Done = 1

Figure 6.11. State diagram for Example 6.1.

Present Next state Outputs
state w=0 w=1

A A B 0 0 0 0 0 0 0
B C C 0 0 1 0 0 1 0
C D D 1 0 0 1 0 0 0
D A A 0 1 0 0 1 0 1

Figure 6.12. State table for Example 6.1.

 Present Next state
state Outputs

B 00 00 01 0 0 0 0 0 0 0
01 10 10 0 0 1 0 0 1 0
C 10 11 11 1 0 0 1 0 0 0
11 00 00 0 1 0 0 1 0 1
D

Figure 6.13. State-assigned table for the sequential circuit in Figure

6.12.
 y2 y1
w
00 01 11 10
0 1
Y 1 = wy1 + y1 y2
1 1 1

y2 y1
w
00 01 11 10
0 1 1
Y 2 = y1 y2 + y1 y2
1 1 1

Figure 6.14. Derivation of next-state expressions for the

sequential circuit in Figure 6.13.
Figure 6.15. Final implementation of sequential circuit in Figure
6.13.
 Next state
Present
state w=0 w=1 Output
Y2 Y1 Y2 Y1 z
y2 y1
A

B 00 00 01 0
01 00 11 0
C 11 00 11 1
10 dd dd d

Figure 6.16. Improved state assignment for the sequential in Figure

6.4. circuit
 Y2 y2
D Q z

Y1 y1
w
D Q

Clock Q

Resetn

Figure 6.17. Final circuit for the improved state

assignment in Figure 6.16.
 Present Nextstate
state Outputs

B 00 00 01 0 0 0 0 0 0 0
01 11 11 0 0 1 0 0 1 0
C 11 10 10 1 0 0 1 0 0 0
10 00 00 0 1 0 0 1 0 1
D

Figure 6.18. Improved state assignment for the sequential

circuit in Figure 6.12.
 y2 y1
w 00 01 11 10
0 1
Y 1 = wy 2 + y1 y2
1 1 1

y2 y1
w
00 01 11 10
0 1 1
Y 2 = y1
1 1 1

Figure 6.19. Derivation of next-state expressions for the

sequential circuit in Figure 6.18.
 Present Nextstate
state w=0 w=1 Output
Y3 Y2 Y1 Y3 Y2 Y1 z
y3 y2 y1
A

B 001 001 010 0

010 001 100 0
C 100 001 100 1

Figure 6.20. One-hot state assignment for the sequential in Figure

6.4. circuit
 Present Nextstate
state Outputs

B 0 001 0001 0010 0 0 0 0 0 0 0

0 010 0100 0100 0 0 1 0 0 1 0
C 0 100 1000 1000 1 0 0 1 0 0 0
1 000 0001 0001 0 1 0 0 1 0 1
D

Figure 6.21. One-hot state assignment for the sequential circuit in

Figure 6.12.
Clock cycle: t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10
w: 0 1 0 1 1 0 1 1 1 0 1
z: 0 0 0 0 1 0 0 1 1 0 0

Figure 6.22. Sequences of input and output signals.

 Reset

w=1z=0

w=0z=0 A B w=1z=1

w=0z=0

Figure 6.23. State diagram of an FSM that realizes the task Figure
6.22. in
Present Next state O utput z
state w = 0 w =1 w= 0 w = 1

A A B 0 0
B A B 0 1

Figure 6.24. State table for the FSM in Figure 6.23.

 Present Next state Output
state w= 0 w =1 w= 0 w= 1

y Y Y z z
A
0 0 1 0 0
1 0 1 0 1
B

Figure 6.25. State-assigned table for the FSM in Figure 6.24.

 z

w
D Q y

Clock Q

Resetn

(a) Circuit

t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10
1
Clock
0
1
w
0
1
y
0
1
z
0

(b) Timing diagram

Figure 6.26. Implementation of FSM in Figure 6.25.

Figure 6.27. Circuit that implements the specification in Figure
6.2.
 w=0

A Reset

w = 1  R2out = 1 R3in = 1

B
w =0
w =1 R1out = 1 R2in = 1

C
w =0
w =1 R3out = 1 R1in = 1 Done = 1

Figure 6.28. State diagram for Example 6.4.

module simple (Clock, Resetn, w, z);
input Clock, Resetn, w;
output z;
reg [2:1] y, Y;
parameter [2:1] A = 2'b00, B = 2'b01, C = 2'b10;

// Define the next state combinational circuit

always @(w, y)
case (y)
A: if (w) Y = B;
else Y = A; B: if (w) Y = C;
else Y = A; C: if (w) Y = C;
else Y = A;
default: Y = 2'bxx;
endcase

// Define the sequential block

always @(negedge Resetn, posedge Clock) if (Resetn = = 0) y <= A;
else y <= Y;

// Define output
assign z = (y = = C);

endmodule

Figure 6.29. Verilog code for the FSM in Figure 6.3.

 Please see “portrait orientation” PowerPoint file for Chapter
6

Figure 6.30. Implementation of the FSM of Figure 6.3 in a

CPLD.
 7 4 1 44 39

10 36

EPM7032
13
z

16
19 22 25 28

Figure 6.31. The circuit from Figure 6.30 in a small

CPLD.
Figure 6.32. Simulation results for the circuit in Figure
6.30.
module simple (Clock, Resetn, w, z);
input Clock, Resetn, w;
output reg z;
reg [2:1] y, Y;
parameter [2:1] A = 2'b00, B = 2'b01, C = 2'b10;

// Define the next state combinational circuit

always @(w, y)
begin
case (y)
A: if (w) Y = B; Y
else = A; Y =
B: if (w) C; Y = A;
else Y = C; Y
C: if (w) = A;
else Y = 2'bxx;
default:
endcase
z = (y = = C); //Define output
end

// Define the sequential block

always @(negedge Resetn, posedge
Clock)
if (Resetn = = 0) y <= A;
elsey <= Y;

endmodule

Figure 6.33. Second version of code for the FSM in Figure 6.3.
module simple (Clock, Resetn, w, z);
input Clock, Resetn, w;
output z;
reg [2:1] y;
parameter [2:1] A = 2'b00, B = 2'b01, C = 2'b10;

// Define the sequential block

always @(negedge Resetn, posedge Clock)
if (Resetn = = 0) y <= A;
else
case (y)
A: if (w) y <= B; y
else <= A; y
B: if (w) <= C; y
else <= A; y
C: if (w) else <= C; y
default: <= A;
endcase y <= 2'bxx;

// Define output
assign z = (y = = C);

endmodule

Figure 6.34. Third version of code for the FSM in Figure 6.3.
Please see “portrait orientation” PowerPoint file for Chapter
6

Figure 6.35. Verilog code for the FSM in Figure

6.11.
Please see “portrait orientation” PowerPoint file for Chapter
6

Figure 6.36. Verilog code for the Mealy machine of Figure

6.23.
Figure 6.37. Simulation results for the Mealy
machine.
Figure 6.38. Potential problem with asynchronous inputs to a Mealy FSM.
 A

a
Shift register
s
Adder
FSM Shift register
Shift register
b
Sum = A + B
B
Clock

Figure 6.39. Block diagram for the serial

adder.
 Reset ab  s
11  0

00  0 01  0
01  1 G H 10  0
10  1 11  1

00  1

G: carry-
in = 0 H:
carry-
in = 1

Figure 6.40. State diagram for the serial adder FSM.

Present Next state Output s
state ab =00 01 10 11 00 01 10 11

G G G G H 0 1 1 0
H G H H H 1 0 0 1

Figure 6.41. State table for the serial adder FSM.

 Next state Output
Present
state ab =00 01 10 11 00 01 10 11
Y s
y

0 0 0 0 1 0 1 1 0
1 0 1 1 1 1 0 0 1

Figure 6.42. State-assigned table for Figure 6.41.

a s
Full
adder Y y
b
carry-out D Q

Clock Q

Reset

Figure 6.43. Circuit for the adder FSM in Figure 6.39.

 Reset

1 01
00 G0  s =0 H0  s =0
1 10

00
01 01
00 1 1
10 10
1 1

01
G1  s = 1 H1  s = 1 1
10 00 1

Figure 6.44. State diagram for the Moore-type serial adder FSM.
 Present Nextstate Output
state ab =00 01 10 11 s

G0 G0 G1 G1 H0 0
G1 G0 G1 G1 H0 1
H0 G1 H0 H0 H1 0
H1 G1 H0 H0 H1 1

Figure 6.45. State table for the Moore-type serial adder FSM.
 Nextstate
Present
state ab =00 01 10 11 Output
y2 y1 Y2 Y 1 s

00 00 01 01 10 0
01 00 01 01 10 1
10 01 10 10 11 0
11 01 10 10 11 1

Figure 6.46. State-assigned table for Figure 6.45.

 Sum bit Y1 y1
a s
D Q
Full adder
Carry-out
b Q

Y2 y2
D Q

Clock Q

Reset

Figure 6.47. Circuit for the Moore-type serial adder FSM.

 module shiftrne (R, L, E, w, Clock,
parameter n Q);
= 8; input [n-1:0]
R; input L, E, w, Clock; output
reg [n-1:0] Q; integer k;

always @(posedge Clock)

if (L)
Q <= R;
else if (E)
begin
for (k = n-1; k > 0; k = k-1) Q[k-
1] <= Q[k];
Q[n-1] <= w;
end

endmodule

Figure 6.48. Code for a left-to-right shift register with an enable input.
Please see “portrait orientation” PowerPoint file for Chapter
6

Figure 6.49. Verilog code for the serial

adder.
Please see “portrait orientation” PowerPoint file for Chapter
6

Figure 6.50. Synthesized serial

adder.
 Equivalence of states

Two states Si and Sj are said to be equivalent if and only if for every possible input
sequence, the same output sequence will be produced regardless of whether Si or Sj is
the initial state.
Present Next state Output
state w= 0 w= 1 z

A B C 1
B D F 1
C F E 0
D B G 1
E F C 0
F E D 0
G F G 0

Figure 6.51. State table for Example 6.6.

 Present Nextstate Output
state w= 0 w= 1 z

A B C 1
B A F 1
C F C 0
F C A 0

Figure 6.52. Minimized state table for Example

6.6.
Clock

sense
N

sense
D

N D

(a) Timing diagram

sense N D Q D Q

Clock Q Q

(b) Circuit that generates N

Figure 6.53. Signals for the vending machine.

 DN

Reset
DN
DN S1  0 DN

DN DN
D N

D
S4  1 N S2  0 S3  0 S7  1

D N
DN

S5  1 S6  0 DN DN

N D

S8  1 S9  1

Figure 6.54. State diagram for Example 6.7.

Present Next state Output
state DN =00 01 10 11 z

S1 S1 S3 S2 – 0
S2 S2 S4 S5 – 0
S3 S3 S6 S7 – 0
S4 S1 – – – 1
S5 S3 – – – 1
S6 S6 S8 S9 – 0
S7 S1 – – – 1
S8 S1 – – – 1
S9 S3 – – – 1

Figure 6.55. State table for Example 6.7.

 Present Next state Output
state DN =00 01 10 11 z

S1 S1 S3 S2 – 0
S2 S2 S4 S5 – 0
S3 S3 S2 S4 – 0
S4 S1 – – – 1
S5 S3 – – – 1

Figure 6.56. Minimized state table for Example

6.7.
 DN

S1  0

N
DN
S3  0
D
DN N DN

D
DN S2  0 S5  1

N
D

S4  1

Figure 6.57. Minimized state diagram for Example

6.7.
 DN  0

S1

N0 D1

DN 
0 S3
N1 D0

N0 D1

S2

DN  0

Figure 6.58. Mealy-type FSM for Example 6.7.

 Present Next state Output z
state w = 0 w =1 w=0 w = 1

A B B C 0 0
C D – 0 –
D E F E 0 1
F G B G 0 0
F C 0 1
E D 0 1
F – 0 –

Figure 6.59. Incompletely specified state table for Example

6.8.
 w=0
w=0 w=0 w=0

w=1 w=1 w=1

A/0 B/1 C/2 D/3

w=1 w=1

H/7 G/6 F/5 E/4

w=1 w=1 w=1

w=0 w=0 w=0 w=0

Figure 6.60. State diagram for the

counter.
Present Next state
Output
state w= 0 w= 1

A A B 0
B B C 1
C C D 2
D D E 3
E E F 4
F F G 5
G G H 6
H H A 7

Figure 6.61. State table for the

counter.
 Next state
Present
state y2 w=0 w = 1Count
y1 y0 Y 2 Y1 Y0 Y2 Y1 Y0z 2 z 1 z 0

B 000 000 001 000

001 001 010 001
C 010 010 011 010
011 011 100 011
100 100 101 100
D
101 101 110 101
110 110 111 110
E 111 111 000 111
F
Figure 6.62. State-assigned table for the
counter.
G
 y1 y 0 y1 y 0
wy2 wy2
00 01 1110 00 01 11 10
00 0 1 1 0 00 0 0 1 1

01 0 1 1 0 01 0 0 1 1

11 1 0 0 1 11 0 1 0 1

10 1 0 0 1 10 0 1 0 1

Y 0 = wy 0 + wy0 Y 1 = wy1 + y1 y0 + wy 0 y1

y1 y0
wy2
00 01 11 10

00 0 0 0 0

01 1 1 1 1
11 1 1 0 1

10 0 0 1 0

Y 2 = wy 2 + y0 y2 + y1 y2 + wy0 y1
y2

Figure 6.63. Karnaugh maps for D flip-flops for the

counter.
Please see “portrait orientation” PowerPoint file for Chapter
6

Figure 6.64. Circuit diagram for the counter

implemented with D flip-flops.
 Flip-flop inputs
Present
state y2 w= 0 w= 1 Count
y1 y 0 Y2 Y1 Y0 J 2 K2 J 1 K1 J0 K0 Y2 Y1 Y0 J 2 K2 J 1 K1 J 0 K 0 z 2 z1 z 0

B 000 000 0d 0d 0d 001 0d 0d 1d 000

001 001 0d 0d d0 010 0d 1d d1 001
C 010 010 0d d0 0d 011 0d d0 1d 010
011 011 0d d0 d0 100 1d d1 d1 011
D 100 100 d0 0d 0d 101 d0 0d 1d 100
101 101 d0 0d d0 110 d0 1d d1 101
E 110 110 d0 d0 0d 111 d0 d0 1d 110
111 111 d0 d0 d0 000 d1 d1 d1 111
F

G
Figure 6.65. Excitation table for the counter with JK flip-flops.
H
Please see “portrait orientation” PowerPoint file for Chapter
6

Figure 6.66. Karnaugh maps for JK flip-flops in the

counter.
 w J Q y0

K Q

y1
J Q

K Q

J Q y2

K Q

Clock
Resetn

Figure 6.67. Circuit diagram using JK flip-flops.

 w J Q y0

K Q

y1
J Q

K Q

J Q y2

K Q

Clock
Resetn

Figure 6.68. Factored-form implementation of the

counter.
 Present Next Output
state state z 2z 1z 0

A B 000
B C 100
C D 010
D E 110
E F 001
F G 101
G H 011
H A 111

Figure 6.69. State table for the counterlike

example.
 Present Next Output
state y2 state Y2
y1 y0 Y1 Y0 z 2 z 1 z 0
000 1 00 000
100 0 10 100
010 1 10 010
110 0 01 110
001 1 01 001
101 0 11 101
011 1 11 011
111 0 00 111

Figure 6.70. State-assigned table for Figure 6.69.

 D Q z2

D Q
z1

D Q
z0

w Q

Figure 6.71. Circuit for Figure 6.70.

 Reset 000

Idle

0xx 1xx

gnt1  g1 = 1

x0x 1xx 01x

gnt2  g2 = 1

xx0 x1x 001

gnt3  g3 = 1

xx1

Figure 6.72. State diagram for the

arbiter.
 Reset r1r2 r3

Idle

r1 r1

gnt1  g1 = 1

r2 r1 r 1r 2

gnt2  g2 = 1

r3 r2 r1r2 r3

gnt3  g3 = 1

r3

Figure 6.73. Alternative style of state diagram for the

arbiter.
Please see “portrait orientation” PowerPoint file for Chapter
6

Figure 6.74. Verilog code for the

arbiter.
 Y1 y1
D Q
z

Q
w

Y2 y2
D Q

Clock Q

Resetn

Figure 6.75. Circuit for Example 6.9.

 Next State
Present
w=0 w=1 Output Next state
state Present Output
y2y1 Y2Y1 Y2 Y1 z state w= 0 w= 1 z

A A B 0
B A C 0
00 00 01 0
C A D 0
01 00 10 0
D A D 1
10 00 11 0
11 00 11 1
(a) State-assigned table (b) State table

Figure 6.76. Tables for the circuit in Example

6.75.
 J1 y1
w J Q
z

K Q
K1

J2 y2
J Q
Clock
K Q
K2
Resetn

Figure 6.77. Circuit for Example 6.10.

 Present Flip-flop inputs
state y2 w=0 w=1 Output
y1 J2 K 2 J1 K 1 J2 K 2 J1 K 1 z

00 01 01 00 11 0
01 01 01 10 11 0
10 01 01 00 10 0
11 01 01 10 10 1

Figure 6.78. The excitation table for the circuit in Figure

6.77.
w D1 y1
D Q
z

T2 y2
T Q

Clock Q

Resetn

Figure 6.79. Circuit for Example

6.11.
 Present Flip-flop inputs
state w= 0 w= 1 Output
y2 y1 T2 D 1 T2 D 1 z

00 00 01 0
01 00 10 0
10 10 01 0
11 10 01 1

Figure 6.80. Excitation table for the circuit in Figure

6.79.
State name

Output signals or 0 (False) 1 (True)

Condition
actions (Moore
type) expression

(a) State box (b) Decision box

Conditional outputs
or actions (Mealy type)

(c) Conditional output

box

Figure 6.81. Elements used in ASM

charts.
Please see “portrait orientation” PowerPoint file for Chapter
6

Figure 6.82. ASM chart for the FSM in Figure 6.3.

 Reset

0
w
1

B
z

0 1
w

Figure 6.83. ASM chart for the FSM in Figure 6.23.

 Reset

Idle

1
r1

0 gnt1 1
0
g1 r1

1
r
2
0 gnt2 1
0
g2 r2

0 1
r3
gnt3 1
0
g3 r3

Figure 6.84. ASM chart for the arbiter FSM in Figure 6.73.
 w1 z1

Inputs Outputs
wn Combinational zm
circuit

yk Yk

Present-state Next-state
variables variables
y1 Y1

Figure 6.85. The general model for a sequential

circuit.
Figure 6.86. State diagram for Example 6.12.
Figure 6.87. State table for the FSM in Figure 6.86.
Figure 6.88. State-assigned table for the FSM in Figure
6.87.
Figure 6.89. An improved state assignment for the FSM in Figure
6.87.
Figure 6.90. FSM that detects a sequence of two zeros.
Figure 6.91. State diagram for Example 6.14.
Figure 6.92. State table for the FSM in Figure 6.91.
Figure 6.93. State-assigned table for the FSM in Figure
6.92.
Figure 6.94. Excitation table for the FSM in Figure
6.89 with JK flip-flops.
Please see “portrait orientation” PowerPoint file for Chapter
6

Figure 6.95. Verilog code for the FSM in Figure

6.86.
Please see “portrait orientation” PowerPoint file for Chapter
6

Figure 6.96. Verilog code for the FSM in Figure

6.91.
Figure 6.97. Parallel-to-serial
converter.
Please see “portrait orientation” PowerPoint file for Chapter
6

Figure 6.98. FSM for parity generation.

 Present Next state
Output
state y2 w = 0 w = 1
y1 Y2 Y1 Y2 Y1 z

00 10 11 0
01 01 00 0
10 11 00 0
11 10 01 1

Figure P6.1. State-assigned table for Problems 6.1 and 6.2.

 w D Q z

Clock Q

D Q

Figure P6.2. Circuit for Problem 6.29.