05/26/2021 Eceg4155: Ch-4 - Year Iv Semester I - Control and Power Stream - Abrha T

Chapter Four: Digital Instruments
05/26/2021 ECEg4155 : ch-4- |Year IV semester I |Control and Power stream | Abrha T. 1
Analog to Digital conversion (ADC)
Direct Compensation
 The input signal is compared with an internally
generated voltage which is increased in steps starting
from zero.
 The number of steps needed to reach the full
compensation is counted. A simple compensation
type is the staircase ramp.
The stair case ramp
 The basic principle is that the input signal is
compared with an internal staircase voltage,
generated by a series circuit consisting of a pulse
generator (clock), a counter counting the pulses and a
digital to analog converter, converting the counter
output into a dc signal.
 As soon as , is equal to , , the input comparator closes
a gate between the clock and the counter, the counter
stops and its output is shown on the display.
Operation of the Circuit
 The clock generates pulses continuously. At
the start of a measurement, the counter is
reset to 0 at time so that the output of the
digital to analog converter (DAC) is also 0.
 If is not equal to zero, the input
comparator applies an output voltage that
opens the gate so that clock pulses are passed
on to the counter through the gate.
 The counter starts counting and the DAC
starts to produce an output voltage
increasing by one small step at each count of
the counter.
 The result is a staircase voltage applied to the
second input of the comparator, as shown in
Fig. 5.9.
• This process continues until the staircase voltage is equal to
or slightly greater than the input voltage .
At that instant the output voltage of the input comparator
changes state or polarity, so that the gate closes and the
counter is stopped.
The display unit shows the result of the count. As each count
corresponds to a constant dc step in the DAC output voltage,
the number of counts is directly proportional to and hence
to .
 By appropriate choice of reference voltage, the step height of
the staircase voltage can be determined.
Successive Approximation ADC
The successive approximation principle can be easily understood using a simple
example; the determination of the weight of an object.
The weight of the object is determined by using a balance and placing the object on one
side and an approximate weight on the other side.
If the weight placed is more than the unknown weight, the weight is removed and
another weight of smaller value is placed and again the measurement is performed.
Now if it is found that the weight placed is less than that of the object, another weight
of smaller value is added to the weight already present, and the measurement is
performed.
If it is found to be greater than the unknown weight the added weight is removed and
another weight of smaller value is added.
In this manner by adding and removing the appropriate weight, the weight of the
unknown object is determined.
The successive approximation DVM works on the same principle.
Successive Approximation DVM

Working Principle
 When the start pulse signal activates the control circuit,
the successive approximation register (SAR) is cleared.
 The output of the SAR is 00000000.
 of the DIA converter is 0.
 Now, if the comparator output is positive.
 During the first clock pulse, the control circuit sets the D7 to
1, and jumps to the half reference voltage.
 The SAR output is 10000000.
 If is greater than , the comparator output is negative and
the control circuit resets D7.
 However, if is greater than the comparator output is
positive and the control circuits keeps D7 set.
 Similarly the rest of the bits beginning from D7 to Do re set
and tested.
 Therefore, the measurement is completed in 8 clock
pulses. Fig. Successive Approximation Type ADC
At the beginning of the measurement cycle, a start pulse is applied
to the start-stop multi vibrator.
This sets a 1 in the MSB of the control register and a 0 in all bits
(assuming an 8-bit control) its reading would be 10000000.
This initial setting of the register causes the output of the D/A
converter to be half the reference voltage, i.e. 1/2 V.
This converter output is compared to the unknown input by the
comparator.
If the input voltage is greater than the converter reference voltage,
the comparator output produces an output that causes the control
register to retain the 1 setting in its MSB and the converter
continues to supply its reference output voltage of 1/2 Vref.
The ring counter then advances one count, shifting a 1 in the second MSB of the control
register and its reading becomes 11000000.
This causes the DIA converter to increase its reference output by 1 increment to 1/4 V, i.e.
1/2 V +1/4 V, and again it is compared with the unknown input.
If in this case the total reference voltage exceeds the unknown voltage, the comparator
produces an output that causes the control register to reset its second MSB to 0.
The converter output then returns to its previous value of 1/2 V and awaits another input
from the SAR.
When the ring counter advances by 1, the third MSB is set to 1 and the converter output
rises by the next increment of 1/2 V + 1/8 V.
The measurement cycle thus proceeds through a series of successive approximations.
Finally, when the ring counter reaches its final count, the measurement cycle stops and the
digital output of the control register represents the final approximation of the unknown
input voltage.
Bits
Operation
V = Output voltage, V
in
Done on Compare Output out
1V D D D D D D D D V_ref = 5 V
bits 7 6 5 4 3 2 1 0
1V D Set
7 1 0 0 0 0 0 0 0 V <V
in out D reset
7 5/2 = 2.5 V
1V D Set
6 0 1 0 0 0 0 0 0 V <V
in out D reset
6 2.5/2 = 1.25 V
1V D Set
5 0 0 1 0 0 0 0 0 V >V
in out D Set
5 1.25/2 = 0.625 V
1V D Set
4 0 0 1 1 0 0 0 0 V >V
in out D Set
4 0.625+(0.625/2)= 0.9375 V
0.625+(0.625/2)+(0.625/4)=
1V D Set 0 0 1 1 1 0 0 0 V <V D reset
3 in out 3
1.09375 V
0.625+(0.625/2)+(0.625/8)=
1V D Set 0 0 1 1 0 1 0 0 V <V D reset
2 in out 2
1.015625 V
1V D Set
1 0 0 1 1 0 0 1 0 V >V
in out D Set
1 0.9765625 V
1V D Set
0 0 0 1 1 0 0 1 1 V >V
in out D Set
0 0.99609375 V
Digital Voltmeters DVM
Ramp Technique:
 At the start of the measurement a
ramp voltage is initiated (counter is
reset to 0 and sampled rate multi
vibrator gives a pulse which
initiates the ramp genera-tor).
Ramp Technique ---------cont’d
 The ramp voltage is continuously compared with the voltage that is being measured.
 At the instant these two voltage become equal, a coincidence circuit generates a pulse which
opens a gate, i.e. the input comparator generates a start pulse.
 The ramp continues until the second comparator circuit senses that the ramp has reached
zero value.
 The ground comparator compares the ramp with ground. When the ramp voltage equals zero
or reaches ground potential, the ground comparator generates a stop pulse.
 The output pulse from this comparator closes the gate. The time duration of the gate opening
is proportional to the input voltage value.
 In the time interval between the start and stop pulses, the gate opens and the oscillator
circuit drives the counter.
 The magnitude of the count indicates the magnitude of the input voltage, which is displayed
by the readout.
 Therefore, the voltage is converted into time and the time count represents the magnitude of
the voltage.
Ramp Technique ---------cont’d

Advantages
 The ramp technique circuit is easy to design and its cost is low.
 Also, the output pulse can be transmitted over long feeder lines.
Disadvantages
 The single ramp requires excellent characteristics regarding linearity of the ramp and
time measurement.
 Large errors are possible when noise is superimposed on the input signal.
 Input filters are usually required with this type of converter
Dual Slope Integrating Type DVM
(Voltage to Time Conversion)
 In ramp techniques, superimposed noise can cause
large errors.
 In the dual ramp technique, noise is averaged out
by the positive and negative ramps using the
process of integration.
Principle of Dual Slope Type DVM
 As illustrated in Fig. 5.3, the input voltage is
integrated, with the slope of the integrator output
proportional to the test input voltage.
 After a fixed time, equal to t1, the input voltage is
disconnected and the integrator input is connected
to a negative voltage er
 The integrator output will have a negative slope
which is constant and proportional to the
magnitude of the input voltage.
 At the start a pulse resets the counter and the F/F
output to logic level ‘0’. Si is closed and Sr is open.
 The capacitor begins to charge. As soon as the
integrator output exceeds zero, the comparator
output voltage changes state, which opens the gate
so that the oscillator clock pulses are fed to the
counter. (When the ramp voltage starts, the
comparator goes to state 1, the gate opens and
clock pulse drives the counter.)
 When the counter reaches maximum count,
i.e. the counter is made to run for a time ‘t 1‘ in this
case 9999, on the next clock pulse all digits go to 0000
and the counter activates the F/F to logic level ‘1’.
This activates the switch drive, e i is disconnected and
–er is connected to the integrator.
Digital Multimeters
Digital Multimeters
Digital Multimeters
 Analog meters require no power supply, they give a better visual indication of changes
and suffer less from electric noise and isolation problems. These meters are simple and
inexpensive.
 Digital meters, on the other hand, offer high accuracy, have a high input impedance and
are smaller in size. They gives an un ambiguous reading at greater viewing distances. The
output available is electrical (for interfacing with external equipment), in addition to a
visual readout.
 The three major classes of digital meters are panel meters, bench type meters and system
meters.
 All digital meters employ some kind of analog to digital (A/D) converters (often dual
slope integrating type) and have a visible readout display at the converter output.
Digital Multimeters
Digital Multimeters ------cont’d
 The basic circuit shown in Fig. 6.2 (a) is
always a dc voltmeter.
 Current is converted to voltage by
passing it through a precision low
shunt resistance while alternating
current is converted into dc by
employing rectifiers and filters.
 For resistance measurement, the
meter includes a precision low current
source that is applied across the
unknown resistance; again this gives a
dc voltage which is digit ised and
readout as ohms.
Digital Multimeters
Digital Multimeters -------cont’d
A basic Digital Multimeters

(DMM) is made up of
several A/D converters,
circuitry for counting and
an attenuation circuit
The current to voltage
converter shown in the
block diagram of Fig. 6.2
(b) can be implemented
with the circuit shown in
Fig. 6.2 (c) below
Digital Multimeters
Digital Multimeters –cont’d
 Resistance is measured
by passing a known
current, from a constant
current source, through
an unknown resistance.
 The voltage drop across
the resistor is applied to
the AID converter,
thereby producing an
indication of the value of
the unknown resistance.
Digital Multimeters
Digital Multimeters –cont’d
 Resistance is measured
by passing a known
current, from a constant
current source, through
an unknown resistance.
 The voltage drop across
the resistor is applied to
the AID converter,
thereby producing an
indication of the value of
the unknown resistance.
Decade Counter
Decade Counter:
 A decade counter is a circuit of flip-flops (F/Fs) in cascade, which counts in
the base 10 (decimal number system).
 This means that there is a sequence of ten distinct counts in increasing order.
 Three F/Fs used in cascade progress through 8 distinct counts (binary
numbers from 000 to 111)
 While 4 F/Fs in cascade progress through 16 distinct states (binary numbers
0000 to 1111).
 Hence to get a count of 10, a minimum of 4 F/Fs are required (because 8
distinct states are less while 16 are too many for a decade counter).
 This problem can be overcome by using 4 F/Fs in Cascade and resetting the
output of each F/F to 0 after the desired 10 counts.
Decade Counter
Decade Counter----cont’d
 The outputs of the F/F B and D
are high (equal to binary 1)
after 10 pulses have been
applied to the counter.
 Therefore, the output signal of
the decade counter is 1010.
 This output has to be reset on
the very next pulse which is
done by the use of an AND gate
that resets all F/F’s to 0, when
the outputs of B and D are 1.
Decade Counter

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Chapter Four: Digital Instruments

Ramp Technique ---------cont’d

 Input filters are usually required with this type of converter

A basic Digital Multimeters

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