Computer Architecture and

Organization (Eeng 3192)

2. The Computer System

 The computer system
• In this chapter:
– Basic Computer Components and Function
– Interconnection Structure
– Bus Interconnection
 Computer components
• Virtually all contemporary computer designs are based on von
Neumann architecture
• Key concepts:
– Data and instructions stored in a single R-W memory
– Contents are addressable by location
– Execution is sequential
• Components reconfigured as application changes (called
programming)
• Resulting “program” – hardwired program
 Computer components
• Another alternative:
– General purpose configuration of components (ALU)
– System accepts data and control signals and produce
results
– New set of control signals instead of rewiring hardware
– how control signals are supplied:
• The entire program is sequence of steps
• For each step, new set of control signals is needed
• Provide a unique code for each possible set of control signals
• The sequence of codes/instructions is called software
 Computer components

• The above two components constitute the CPU

• Other components:
– I/O components: for moving data into and out of system
– Memory: to store instructions and data temporarily
 Computer components
• Central Processing Unit
– Control Unit
– Arithmetic and Logic Unit
– Registers
• Input/output
– Data and instructions need to get into the system and
results out
• Main Memory
– Temporary storage of code and results is needed
• Interconnection structures
– Bus
Computer components
 Computer function
• Basic function: execution of a program
• Two steps of program execution:
– Fetch
– Execute
• Instruction cycle – the processing required for a
single instruction (i.e fetch and execute cycles)
 Instruction cycle
• Fetch cycle
– Program Counter (PC) holds address of next instruction to
fetch
– Processor fetches instruction from memory location pointed
to by PC
– Increment PC
• Unless told otherwise
– Instruction loaded into Instruction Register (IR)
– Processor interprets instruction
– Instructions contain bits that specify action the processor is to
take
– These actions fall into 4 categories:
 Instruction cycle
• Execute cycle:
– Processor-memory
• Data transfer between CPU and main memory
– Processor I/O
• Data transfer between CPU and I/O module
– Data processing
• Some arithmetic or logical operation on data
– Control
• Alteration of sequence of operations
• e.g. jump
– Instruction execution may involve combination of the
above
 Example of Program Execution
• Example – consider the following machine:
 Example of Program Execution
• Program:
AC ← M(940)
AC ← AC + M(941)
M(941) ← AC
Instruction Cycle State Diagram
 Interrupts
• Interrupt
– Mechanism by which various events (e.g. I/O) may
interrupt normal sequence of processing
– Classes of interrupts:
− Program
− Overflow, division by zero, etc.
− Timer
− Generated by internal processor timer
− Used in pre-emptive multi-tasking
− I/O
− From I/O controller
− Hardware failure
− Memory parity error, etc.
Interrupts
Instruction cycle with interrupt
 State diagram with interrupt

Reading Ass.: more on interrupts – text, pp 64-73

 Interconnection Structures
• All the components should be connected
• Collection of paths connecting modules
• Design depends on exchanges made b/n modules
• Different type of connection for different type of unit
– Memory
– Input/Output
– CPU
 Interconnection Structures
• Memory connection
– Receives:
− Data
− Addresses (of locations)
− Control signals
− Read
− Write
− Timing
− Sends
− Data
 Interconnection Structures
• I/O connection
– Receives
− Control signals from computer
− Addresses from computer
− e.g. port number to identify peripheral
− Data from computer
− Data from peripheral
– Sends
− Control signals to peripherals
− e.g. spin disk
− Data to peripherals
− Data to computer
− Control signals to computer
− interrupts
 Interconnection Structures
• CPU connection
– Receives
− Instructions
− Data
− Control
− interrupts

– Sends
• Data
• Address
• Control signals to other units
 Interconnection Structures
• The interconnection structure must support the
following types of transfers:
– Memory to processor: processor reads instruction or a
unit of data from memory
– Processor to memory: processor writes a unit of data to
memory
– I/O to processor: processor reads data from I/O device via
I/O module
– Processor to I/O: processor sends data to I/O device
– I/O to/from mem: I/O module exchanges data directly
with memory (DMA)
 Bus Interconnection
• Various interconnection structures have been tried
• Most common – a single bus or multiple bus structures
• Examples:
− Control/Address/Data bus (PC)
− Unibus (DEC-PDP)

− BUS:
− Communication pathway connecting two or more devices
− Usually broadcast
– Often grouped
• A number of channels in one bus
• e.g. 32 bit data bus is 32 separate single bit channels
− Power lines may not be shown
Bus Interconnection Scheme
 Bus Interconnection
• Data bus:
– Carries data
• Remember – no difference between “data” and
“instruction” at this level
– Bus width
− key determinant of performance
− typically 8, 16, 32, 64 bit
 Bus Interconnection
• Address bus:
– Identifies the source or destination of data
• e.g. CPU needs to read an instruction (data) from a
given location in memory
• Also used to address I/O ports
• Bus width
− determines maximum memory capacity of system
− e.g. 8080 has a 16 bit address bus giving 64k address
space
 Bus Interconnection

• Control bus
– Control and timing information
− Memory read/write signal
− I/O read/write signals
− Bus arbitration signals – requests, grants
− Interrupt signals – requests, acknowledgments
− Clock signals
 General Bus Operation

• Send data
− Obtain use of bus
− Transfer data
• Request data
− Obtain use of bus
− Transfer request for data
− Wait for data
 Physical Bus Architecture

• What do buses look like?

− Parallel lines on circuit boards
− Ribbon cables
− Strip connectors on mother boards
− e.g. PCI
− Sets of wires
Physical Bus Architecture
 Single Bus Problems

• Lots of devices on one bus lead to:

− Increased bus length
− Propagation delays
− Complex, time consuming coordination of bus
use
− Bus becomes bottleneck
− aggregate data transfer approaches bus capacity

• Solution – multiple buses

Traditional Bus (with cache)
High Performance Bus
 readings
• Text:
– Chapter 3, 73-94