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  • EE-307 Fpga Based System Design: Lecture # 06

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    Talha Khalid
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    This document summarizes a lecture on combinational logic in Verilog. It discusses sensitivity lists and provides examples of using case statements and if/else statements to model a 4-to-1 multiplexer at the behavioral level in Verilog. It also provides the symbol for a 4-to-1 multiplexer and examples of behavioral models using case statements and if statements. Finally, it provides an assignment for students to model a 7-segment display using both dataflow and behavioral modeling in Verilog, and to simulate and take screenshots of both models.

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    This document summarizes a lecture on combinational logic in Verilog. It discusses sensitivity lists and provides examples of using case statements and if/else statements to model a 4-to-1 multiplexer at the behavioral level in Verilog. It also provides the symbol for a 4-to-1 multiplexer and examples of behavioral models using case statements and if statements. Finally, it provides an assignment for students to model a 7-segment display using both dataflow and behavioral modeling in Verilog, and to simulate and take screenshots of both models.

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    7 views13 pages

    EE-307 Fpga Based System Design: Lecture # 06

    Uploaded by

    Talha Khalid
    This document summarizes a lecture on combinational logic in Verilog. It discusses sensitivity lists and provides examples of using case statements and if/else statements to model a 4-to-1 multiplexer at the behavioral level in Verilog. It also provides the symbol for a 4-to-1 multiplexer and examples of behavioral models using case statements and if statements. Finally, it provides an assignment for students to model a 7-segment display using both dataflow and behavioral modeling in Verilog, and to simulate and take screenshots of both models.

    Copyright:

    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd
    Flag for inappropriate content
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    of 13

    EE-307

    FPGA BASED SYSTEM DESIGN


    Spring 2015

    Verilog
    Combinational Logic in Verilog

    Lecture # 06
    Today’s Lecture

     Behavior modeling
     Sensitivity list
     MUX Example
    Multiple ways of defining sensitivity list
    Useful Syntax
    Group multiple statements using begin and end keywords

    always@(sel or in0 or in1)


    begin

    case (sel) if (sel == 1’b0) if (sel == 1’b0)


    1'b0: out = in0; out = in0; begin
    1'b1: out = in1; else out = in0;
    endcase out = in1; a = 1’b0;
    end
    case (sel) if (sel == 1’b0) else if (sel == 1’b1)
    1'b0: begin begin
    begin out = in0; out = in1;
    out = in0; a = 1’b0; a = 1’b1;
    a = 1’b0; End end
    end
    1'b1: else
    begin begin
    out = in1; out = in1;
    a =1’b1; a = 1’b1;
    end end
    endcase WARNING
    DEFAULT is MUST in CASE
    end
    Lectures

     We know the following


     Gate Level
     Gate primitives (and, or, not, xor, xnor etc.)
     Dataflow
     Assign Statement
     Operators & Conditional Statement
     Behavioral Block
     Allows use of higher level constructs (if-else, case, loops) in
    ALWAYS (synthesizable) or INITIAL BLOCKS (non-
    synthesizable)
     Sensitivity List
    Combinational Logic Building Blocks
    & their Verilog Coding Examples
    @ Behavioural Level
    Multiplexers
     n input datapath; single output datapath
     MUX/DEMUX establish dynamic connectivity b/w
    datapaths
     Data Routing, e.g. Selecting data from different sources
     Example: Selecting data from Functional units in a CPU based upon the
    instruction
     Time Division Multiplexing
    Multiplexer [4to1]

    Symbol
    Behavioural Model
    4 channel using CASE

    module mux_case(sel,in1,in2,in3,in4,out1);

    input [1:0] sel;


    input in1,in2,in3,in4;
    output reg out1;

    always @ (sel,in1,in2,in3,in4)
    begin

    case (sel) // Put the case parameter in brackets


    2'b00: out1 = in1;
    2'b01: out1 = in2;
    2'b10: out1 = in3;
    2'b11: out1 = in4;
    default : out1 = 1'b0;
    endcase // Don’t Forget, else error 

    end
    endmodule
    Behavioural Model
    4 channel 32 bit MUX – using IF
    MUX

    http://www.electronicsnews.com.au/technical-articles/best-design-practices-for-high-capacity-fpga-devic
    Assignment
     Write Verilog code for 7 segment Display using
     Dataflow modeling &
     Behavior modeling

     Make two Verilog files for behavior & dataflow. Each


    will have its own module.

     Write stimulus and instantiate the both module in


    single stimulus. Run simulation in Modelsim and take
    printscreen of waveforms.
    DEMO

     Modelsim
     Xilinx ISE (Introduction)

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