Basic Concepts Of DSM:

⦿ A DSM system provides a logical abstraction of

shared memory which is built using a set of
interconnected nodes having physically
distributed memories.
Types of DSMs
⦿ Hardware level DSM
⦿ Software level DSM
⦿ Hybrid level DSM
Advantages of DSM
⦿ Simple abstraction
⦿ Improved portability of distributed
application programs
⦿ Provides better performance in some
applications
⦿ Large memory space at no extra cost
⦿ Better than message passing systems
 Comparison of IPC
paradigms
 DFS
⚫ Single shared address space
⚫ Communicate, synchronize using load / store
⚫ Can support message passing

 Message Passing
⚫ Send / Receive
⚫ Communication + synchronization
⚫ Can support shared memory
Hardware architectures
⦿ On chip memory
⦿ Bus based multiprocessor
⦿ Ring based multiprocessor
⦿ Switched multiprocessor
 On chip memory
In this CPU portion of the chip has a address and data lines that directly
connect to the memory portion.
Such chips are used in cars appliances and even toys
Bus based multiprocessor
All CPUs connected to one bus (backplane)
Memory and peripherals are accessed via shared bus. System looks the
same from any processor.
Consistency protocols
Ring DSM architecture
⦿ Shred memory :
⚫ Private areas
⚫ Shared areas
(Ring) Memnet: Node memory
Switched multiprocessor:
⦿ Multiple clusters interconnected by a bus offer better
scalability
⦿ Example : Dash system
NUMA
Multiprocessor
⦿ Non-uniform memory access (NUMA) is a
computer memory design used multiprocessing,
where the memory access time depends on the
memory location relative to the processor.
⦿ Under NUMA, a processor can access its own
local memory faster than non-local memory.
⦿ The benefits of NUMA are limited to particular
workloads, notably on servers where the data is
often associated strongly with certain tasks or users.
UMA
Multiprocessor
⦿ Uniform memory access (UMA) is a shared memory
architecture used in parallel computers. All the processors in
the UMA model share the physical memory uniformly.
⦿ In a UMA architecture, access time to a memory location is
independent of which processor makes the request or which
memory chip contains the transferred data.
⦿ Uniform memory access computer architectures are often
contrasted with non-uniform memory access (NUMA)
architectures.
⦿ In the UMA architecture, each processor may use a
private cache. Peripherals are also shared in some
fashion.
⦿ The UMA model is suitable for general purpose and time
sharing applications by multiple users. It can be used to speed
up the execution of a single large program in time- critical
applications.
D/f b\w two Multiprocessor:
BUS BASED
MULTIPROCCESOR
S S
⦿ They are tightly coupled
with the CPU’S normally
in a single rack.
⦿ It has separate global
memory
RING BASED
MULTIPROCCESOR
⦿ Machines here can be
much more loosely
coupled and this loose
coupling can affect their
performance.
⦿ It has no separate
global memory.
DSM design issues
⦿ Granularity of sharing
⦿ Structure of data
⦿ Consistency models
⦿ Coherence protocols
Granularity
⦿ False sharing
⦿ Thrashing
Thrashing:
⦿ False sharing
⦿ Techniques to reduce
thrashing:
⚫ Application controlled
lock
⚫ Pin the block to a node
for
specific time
⚫ Customize algorithm to
shared data usage pattern
DSM structure
⦿ Organization of data items in the shared
memory
Consistency models
//Important.

⦿ Refers to how recent the shared memory updates are

visible to all the other processes running on different
machines
Strict consistency
⦿ Strongest form of consistency.
⦿ All write operations are visible to all
processes.
Sequential consistency
⦿ All processors in the system observe the same
ordering of reads and writes which are issued in
sequence by the individual processors
Causal consistency
⦿ Weakening of sequential consistency for
better concurrency
⦿ Causally related operation is the one which has
influenced the other operation
PRAM consistency
⦿ Pipelined Random Access Memory consistency
⦿ Write operations performed by different processes may
be seen by different processes in different orders
⦿ All write operations of a single process are pipelined
⦿ Simple, easy to implement and has good performance.
Processor consistency
⦿ Adheres to the PRAM consistency
⦿ Constraint on memory coherence
⦿ Order in which the memory operations are
seen by two processors need not be
identical, but the order of writes issued by
each processor must be preserved
Weak consistency
⦿ Use a special variable called the
synchronization variable.
⦿ Very difficult to show and keep track of the changes
at time to time.
Properties of the weak
consistency model:
⦿ Access to synchronization variables is
sequentially consistent.
⦿ Only when all previous writes are
completed everywhere, access to
synchronizations variable is allowed.
⦿ Until all previous accesses to
synchronization variables are performed, no
read write data access operations will be
allowed.
Release consistency
 Uses two synchronization variables (Acquire and
Release)
 Release consistency model uses synchronization
mechanism based on barriers.
Eager Release
Consistency(ERC)
Lazy Release
Consistency(LRC)
Entry consistency
• Use acquire and release at the start and end
of each critical section, respectively.
• Each ordinary shared variable is
associated with some synchronization
variable such as a lock or barrier.
• Entry consistency (EC) is similar to LRC but
more relaxed; shared data is explicitly
associated with synchronization primitives
and is made consistent when such an
operation is performed
Scope consistency
⦿ A scope is a limited view of memory with
respect to which memory references are
performed
Comparison of consistency
models-1
⦿ Mostcommon: sequential consistency
model .
Comparison of Consistency
models-2
⦿ Based on efficiency and programmability
Coherence protocols
⦿ Specifies
how the rules set by the
memory consistency model are to be
implemented