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CH 4
CH 4
CH 4
Boylestad
DC Biasing - BJTs
Chapter 4
Biasing
Operating Point
The DC input
establishes an
operating or
quiescent point
called the Q-point.
DC Biasing Circuits
Fixed-bias circuit
Emitter-stabilized bias circuit
Collector-emitter loop
Voltage divider bias circuit
DC bias with voltage feedback
Fixed Bias
VCC VBE
IB
RB
Collector-Emitter Loop
Collector current:
IC IB
VCE VCC IC RC
Saturation
V
ICsat CC
R
C
VCE 0 V
Base-Emitter Loop
From Kirchhoff’s voltage law:
VCC IE RE VBE IE RE 0
Since IE = ( + 1)IB:
VCC IB RB (β 1)I B RE 0
Collector-Emitter Loop
From Kirchhoff’s voltage law:
I E RE VCE I C RC VCC 0
Since IE IC:
VCE VCC – I C(RC R E )
Also:
VE I E RE
VC VCE VE VCC IC RC
VB VCC – I R RB VBE VE
Saturation Level
Saturation:
V
I CC
C R R
C E
VCE 0 V
Base-Emitter Loop
From Kirchhoff’s voltage law:
VCC – IC RC –IB RB –VBE –IE RE 0
VCC VBE
Solving for IB: IB
RB β(RC RE )
Collector-Emitter Loop
Applying Kirchoff’s voltage law:
To ensure saturation:
ICsat
IB
βdc
Emitter-collector
resistance at VCEsat VCC
Rsat Rcutoff
saturation and cutoff: ICsat ICEO
Switching Time
t on t r t d
t off t s t f
Troubleshooting Hints
Approximate voltages VBE .7 V for silicon transistors
VCE 25% to 75% of VCC
PNP Transistors