Professional Documents
Culture Documents
Lec4.4 Power Descipation
Lec4.4 Power Descipation
Lec4.4 Power Descipation
4
POWER DESIPATION
Engr. Anees ul Husnain ( anees.buzdar@gmail.com )
T T
C
fsw
Dynamic power dissipation
Vdd
CL
If the gate is switched on and off f01 (switching factor) times per second,
the power consumption is given by
Pdynamic CVDD f 2
Short circuit current
When transistors switch, both nMOS and pMOS networks may be momentarily
ON at once
< 10% of dynamic power if rise/fall times are comparable for input and output
Techniques for low-power design Pdynamic CVDD 2 f
Clock
Enable
Clock Gating
Dynamic power reduction via dynamic VDD scaling
Supply and voltage of the circuit should dynamic adjust according to the
workload of criticality of the tasks running on the circuits
1. Oxide thickness
I1
I2 O1
I3
I4
I5 O2
I critical
6 path
Static (leakage) power
Vgs Vt
Vds
I ds I ds 0e nvT
1 e
vT
Leakage Control
Leakage and delay trade off
Aim for low leakage in sleep and low delay in active mode
To reduce leakage:
Increase Vs: stack effect (series OFF transistors have less leakage)
Input vector control in sleep
Decrease Vb
Reverse body bias in sleep
Or forward body bias in active mode
Gate Leakage