IMAGE EDGE DETECTION

BASED ON FPGA

Batch No: 1106

Presented By:
A.SARITHA 07121A0402
A.MIDHUN 07121A0457
S.PAVAN KUMAR 07121A0474
M.UDAY 07121A0455
G.SIDDARTHA 07121A0430

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

SREE VIDYANIKETHAN ENGINEERING COLLEGE
(Autonomous)
SREE SAINATH NAGAR,A.RANGAMPET,
TIRUPATHI-517102
 CONTENTS
• Objective
• Existing and proposed system
• Introduction to edge detection
• Sobel operator and need for FPGA
• Project overview
• Module-1,Module-2 and Module-3
• Algorithm
• Results
• Applications
• References
 Objective
This project presents a kind of parallel processing
construction of edge detection algorithm.
The edge of the grey image can be located
efficiently.
 Image analysis is to distinguish and count
objects, and recognize the shape of objects from
an image.
A solution to implement complex algorithms at
faster frame rates is to build custom hardware.
 Existing system
EXISTING SYSTEM
• In the existing conventional segmentation
techniques, intensity values used for
thresholding are not detected properly and
result in segmentation errors.
• This processing can be performed on an FPGA
rather than a microprocessor or DSP.
 PROPOSED SYSTEM

PROPOSED SYSTEM:
Sobel Edge detection is implemented in
FPGA due to its programming flexibility.
 Edges and edge detection
  EDGES:
• Edges are those places
in an image that
correspond to object
boundaries.
• Edges are pixels where
image brightness
changes abruptly.
Brightness vs. Spatial
Coordinates
 EDGE DETECTION?
• An edge is an abrupt change in brightness as we
move from one pixel to its neighbor in an image.
• Edge information for a particular pixel is obtained
by exploring the brightness of pixels in the
neighborhood of that pixel.
• If all the pixels in neighborhood are of same
brightness levels means no edge, if there is
change in brightness there is more chance of an
edge.
 Comparing Edge Operators
Good Localization
Gradient: Noise Sensitive
Poor Detection
Roberts (2 x 2): 0 1 1 0
-1 0 0 -1

Prewitts (3 x 3):
-1 0 1 1 1 1
-1 0 1 0 0 0
-1 0 1 -1 -1 1

Poor Localization
Less Noise Sensitive
Good Detection
 Gradient Methods – Sobel Operator

• The 3X3 convolution mask smoothes the image by some amount , hence
it is less susceptible to noise.
• Convolution Mask

Gx =
-1
Gy=
0 1 1 2 1
-2 0 2 0 0 0
-1 0 1 -1 -2 -1

• The differences are calculated at the center pixel of the mask.

• The gradient is calculated by using he sobel operator for each pixel in the
picture.
• If the absolute value exceeds a threshold, the pixel belongs to an edge.
 WHY SOBEL
• Because of its weighted coefficient ,it is
immune to noise
• The accuracy rates are high when compared
to other gradient methods
 Hardware Module

SRAM

FPGA
Power Supply SPARTAN 3 UART
3.3V XC3S200

Clock
50MHZ
 Why FPGA?

Existing System Proposed System

 DSP processors  FPGA

Disadvantages Advantages
 Inflexible architecture o Parallel design methodology
 Fixed data width o Reconfigurable
 Limited number of MAC units o Implement designs at gate level
 Time-shared MAC unit o MAC capability
 Serial processing limits data o Low power Dissipation
throughput
o Small in size
 Multiple DSPs required to meet
bandwidth needs
 Need for FPGA

Low power Dissipation

Small in size
Accuracy
Floating point
Supports parallelism
Easily reconfigurable
Can implement larger logic funcions.
FPGA – Spartan-3 XC3S200
 220K system gates, 4320 equiv. logic cells
 480 total CLB (configurable logic block)
 30K distributed RAM bits
 216K block RAM bits
 12 dedicated multipliers
 4 DCM (digital clock multiplier)
 173 user I/O, 76 differential I/O pairs

CONFIGURABLE LOGIC BLOCK

 Main logic resource for implementing
synchronous and combinatorial circuits
 Comprised of four slices
 Two logic function generators, two storage
elements, wide-function multiplexers, carry
logic, and arithmetic gates
 left-hand pair also supports: storing data
using Distributed RAM and shifting data with
16-bit registers.
 Control system For FPGA
FPGAs are programmable digital logic chips. We can
program them to do almost any digital function.
We can compile the "logic function" on your
computer, using a software provided by the FPGA
vendor that creates a binary file that can be
downloaded into the FPGA.
We can connect a cable from the computer to the
FPGA, and the binary file can be downloaded to the
FPGA.
That's it! our FPGA behaves according to our "logic
function".
 Project Overview
Module 1: Conversion of the input image
into text file format using Matlab.

Module 2: Developing custom logic &

Softcore processor design.

Module 3: Configuration into FPGA using

EDK.
 Module 1

Input 2-D Mat lab 1-D Text

image pixels GUI pixels files
 How to read an image

a =imread('cameraman.tif'); a =imread('flowers.tif');
imshow(a); imshow(a);
pixval on; pixval on;
 Convert Image into One dimensional

a = imread('cameraman.tif');

[r c]=size(a);

Len=r*c;

b=reshape(a,[1 Len]);
 Graphical User Interface

• GUI is a user interface built with graphical objects

• MATLAB implements GUIs as figure windows

• MATLAB generates an M-file that contains code to

handle the initialization and launching of the GUI
• This M-file provides a framework for the
implementation of the callbacks
Module 2 -Development tool
 Embedded Development
Tool Flow Overview
Standard Embedded SW Standard FPGA HW
Development Flow Development Flow
C Code VHDL/Verilog

Compiler/Linker Synthesizer
(Simulator) Simulator

Object Code Place & Route

Data2MEM
? ?
CPU code in CPU code in
Bitstream
off-chip on-chip
memory memory Download to FPGA

Download to Board & FPGA

Debugger
 XPS Functions
• Platform
 Project management management
◦ MHS or MSS file – Tool flow settings
◦ XMP file
– Software platform
 Software application settings
management – Debug and
simulation

Hardware HW/SW
Design Simulation

XPS
Software
HW/SW
Design
Debug
 LOGIC BEHIND THE CODE
K1 K2 K3 R1 R2 R3

K4 K5 K6 R4 R5 R6

K7 K8 K9 R7 R8 R9

KERNEL PICTURES

The coefficients of the kernel are multiplied with the pixel

values of the image taking the center pixel as R5
The resultant values are added
FOR EXAMPLE:
Y=(R1*K1)+(R2*K2)+(R3*K3)+………+(R9*K9)
If the pixel output value is greater than the threshlod ,the pixel
is detected as the edge
 ALGORITHM
• Start
• Read the pixel values and Kernel values
• Perform the calculations(multiplicaton followed by addition)
• Compare the output with threshhold
• If
output>threshold
edge pixel is considered
• End if
 FLOW CHART

Start 11

Read the pixel and

kernal values If
if
output>threshold

Edge pixel
Perform the calculation detected

stop
1
 Configuring the FPGA
• Download the bit stream
– Input file → download. bit
– This downloads the download. bit file onto the target
board using the Xilinx impact tool
– XPS uses the etc/download.cmd file for downloading the
bit stream.

EDK Intro 27
 DOWNLOADING THE BITSTREAM
• For downloading the bit stream launch XMD
and type “dow executable. elf”.
• This will be successful only when .elf file is
generated.
 Running and detecting the edge
• After a selecting the textfile from VB, type
“run” in the XMD.
• The text file is nothing but the input image
which is converted using MATLAB .
• The image edges will then be detected once
the run command is entered.
Launching XMD
Input Image for Edge Detection
Edge Detected Output
 Tools used
Software
 Xilinx ISE 8.1i
 Xilinx Platform Studio
 Matlab
 Visual basic

Hardware
 FPGA Spartan3

Language used : VHDL & C

 Applications
• Enhancement of noisy images – satellite
images, x-rays, medical images like cat scans
• Text detection
• Mapping of roads
• Video surveillance, etc.

September 13, 2005 EE - 6358 Computer Vision 35

 CONCLUSION
• The edge of the Image can be effectively
detected using Sobel operator apart from the
various Gradient operators.
• The result of the complex image can be
obtained at higher rates by using FPGA instead
of DSP Processors.
• The Sobel operator adding the orientation of
the convolution kernels can locate accurately
the edge, and not be sensitive to noise.
 REFRERENCES
[1] P. Athanas and A. Abbott. Real-time image processing on acustom
computing platform. In IEEE Computer, Feb. 1995.
[2]2010 Ninth International Symposium on Distributed Computing and
Applications to Business, Engineering and Science.
[3] Chanda, B. and Dutta, D. Majumdar. (2001). Digital Image Processing
and Analysis,Prentice-Hall of India.
[4] Gonzalez, Rafael C. and Woods, Richard E. (2002). Digital Image
Processing, Pearson inc.
[5] D. T.Saegusa, T.Maruyama, Y.Yamaguchi, “How fast is an FPGA in
image processing?”, IEICE Technical Report,Vol.108. No.48, 2008,
pp.83–88
[6] Yangli ,Yangbing. “Study of FPGA based Parallel Processing of Sobel
Operator” AI Modern Electronics Technique 2005.J.
THANK YOU