HIGH SPEED VEDIC

MULTIPLIER FOR DSP’S

PRESENTED BY ,

MANISH KUMAR
EC-A , S7
SOE , CUSAT
 Vedic mathematics ?
 Ancient Indian s/m of mathematics.

 Based on 16 principles called as ‘sutras’.

 Derived from word ‘Veda’ means “store house of all

knowledge”.

 Directly applied to trigonometry , calculus, plain ,

spherical , conics and applied maths of various kinds.
 21 x 13=273 123 x 321=39483
2
. . . . 3 . . . . . .
. . . .
. . . . . .
. . . . . . . . . .
7 3 8
. . . . . .
. . . . . .
. . . . . . 3
(1) 4 8
 EXAMPLES:

98 * 97 = 9506
-2 -3

104 x 103=10712

+4 +3

(96)^2 =9216
-4

221013/ 9=24557
1 (9)
24556
CONTD…
 32142 /9 =3571
11 3
3560 (12)
 NEED OF VEDIC MULTIPLIERS ?

 For low power and high speed applications.

 Generating all partial products and their sums in one

step.

 By using Vedic multiplication algorithm it can be used in

digital signal processing.

 Reduces complexity of calculations to a very simple

way.
 INTRODUCTION

 High speed arithmetic operations are very important in

many signal processing applications.

 Speed of multiplier determines speed of DSPs.

 Multipliers are used in F.T & convolutions.

 multiplications take huge time , an improvement in

multiplication speed can greatly improve s/m
performance.

 Multiplication by algorithms such as array , booth , carry

save and Wallace tree can be implemented.
 ARRAY MULTIPLIERS :

o Less computational time , as partial products

computed independently in parallel.

o delay associated to form the multiplication array.

o Matrices must have same dimension.

o Dimensions of resulting matrix are same as two

multiplied matrices.

o Element wise multiplication.

CONTINUED:
 EXAMPLE:

a= 1 2 3
1 2 3

b= 1 2 3 note:
4 5 6 .* multiply
./ divide
c =a.*b .’ transpose
.^ array power
c= 1 4 9
4 10 18
 ARRANGEMENT OF ADDERS:
 Way to improve multiplication speed.

 Two methods :
i) Carry save array (CSA) method :

• bits are processed one by one to supply a carry s/l to an adder

located at one bit higher position.
• Execution time depends on no. of bits of multiplier.

ii) Wallace tree method :

* 3 bit s/l passed to a full adder , and the sum is supplied to next
stage full adder .
 Carry o/p is passed to next stage FA and then formed
carry is supplied to next stage of FA located at a one bit
higher position .

 FA provides 3:2 compression in the no. of bits.

 For a 32 bit multiplier ,9 adders delay in array.

 Circuit layout is not easy .

7 BITS WALLACE TREE ADDITION
 BOOTH ALGORITHM :
Reduces
 the number of partial products.

High
 speed multiplication and exponential operations needs large
booth arrays which demands large sum and carry registers.

Large
 propagation delay can be minimised .

Fast
 multiplication

Signed
 multiplication
 If there is the sequence of 0’s the multiplication can be
skipped.
 A fast multiplier adopting the sutra of ancient Indian
Vedic Mathematics called “URDHVA
TRIYAKBHYAM”.

 Faster than existing multipliers.

 URDHVA TIRYAKBHYAM
 Means vertically and crosswise algorithm

 mathematic multiplication formula from vedic

mathematics

 Rediscovered by jagadguru swami shri Bharati

Krishna Trithaji maharaja

 Formulae taken from appendix of Atharvaveda.

Multiplication by urdhva triyakbhyam
 DECIMAL MULTIPLICATION

 345 result =15

543 previous carry= 0
15 (1)5

345 result=32
543 previous Carry= 1
(3)3

345 result=5*5+ 3*3+4*4=50

543 previous carry = 3
(5)3
345 result=32
543 previous carry= 5
(3)7

345 result=15
543 previous carry= 3
(1)8

345x543=187335
VEDIC MULTIPLICATION OF BINARY NO.
S/M :
Thus we get the following expressions:

r0 = a0b0
c1r1 = a1b0 + a0b1
c2r2 = c1 + a2b0 + a1b1 + a0b2
c3r3 = c2 + a3b0 + a2b1 + a1b2 + a0b3
c4r4 = c3 + a3b1 + a2b2 + a1b3
c5r5 = c4 + a3b2 + a2b3
c6r6 = c5 + a3b3
CKT IMPLEMENTATION BY LOGIC GATE :
 ARCHITECTURE
DETAILS:
 Fieldprogrammable logic arrays based on the
virtex - 2 architecture.

 Includes memory resources , multipliers , clock

buffers, programmable interconnect and i/o
blocks.

 Slices
contain combinational logic and register
resources.
 VIRTEX– 2 ARCHITECTURE ( INTERNAL )

i/o blocks

--CLBS

CLK MANAGEMENT
Pgm interconnect
BLOCK DGM IMPLEMENTATION OF
DESIGN STEPS IN FPGA:
 STEPS:

 Two major hdl languages are VHDL and VERILOG. Vhdl is

more precise while verilog is similar to ‘C’ language.

 Writing a test environment:-

=>Almost impossible to create a fully correct HDL design. So it
can be tested for possible errors . A pgm can be tested in the
software by writing test environment in ‘HDL’ or in ‘C’.
=>A test environment usually includes a behavioral
modelling.

 Behavioral simulation used to verify hdl description .most of the

design errors are fixed at this stage.
.
 Synthesis is a process of converting a high level hdl
discription to a machine readable ckt discription called
netlist. Some errors uncaught by behavioral simulation
can be fixed at this stage

 Implementation is a process of converting netlist to an

fpga configuration bit-stream.

 Post implementation simulation is used to verify the

implemented design(taking switching and propagation
delays into account)against behavioral model.

 Testing a produced bit-stream in hardware.

 MULTIPLIER ARCHITECTURE
 Partial product and their sum calculated in parallel.

 It makes the multiplier clock independent.

 Advantages over other multipliers are its regularity so , easy layout design will
be possible.

 Consider multiplier and multiplicand are eight bit numbers.

 They are splitted into 4 bit blocks.

 The 4 bit blocks are again divided into 2 bit multiplier blocks.

 Based on ‘urdhva triyakbhyam’ formulae.

Eg:
A=A7A6A5A4A3A2A1A0;
B=B7B6B5B4B3B2B1B0;

A= AH-AL ; B=BH-BL;
AH=A7A6A5A4;
AL=A3A2A1A0;
BH=B7B6B5B4;
BL=B3B2B1B0;
By the algorithm , the product can be written as:

Product of A*B=AL*BL+AH*BL+AL*BH+AH*BH ;
PARALLEL MULTIPLICATIONS:
The 4*4 bit multiplication can be reduced to 2*2 bit
multiplications.

AH=AHH-AHL ; BH=BHH-BHL ;

AH*BH=AHL*BHL+AHH*BHL+AHL*BHH+
AHH*BHH ;

So , any N*N multiplication can be implemented by using

basic 2*2 multipliers units.
Comparision with modified booth wallace multiplier

:
*Vedic multiplier – combinational delay in various devices ( ns )

*Modified booth Wallace multiplier - combinational delay in various

devices ( ns )
 ADVANTAGES
 The highest performances for both multipliers are seen
for Virtex-2p.

 Delays for 8*8 multiplications are approx same for both

but for 16*16 multiplications the Vedic multipliers show
a very improved performance.

 So , Vedic multipliers are extreme fast and is well ahead

of the modified Booth Wallace multipliers.
 conclusions
 Proves to be highly efficient in terms of speed.

 Due to regular and parallel structure it can be

easily realized on silicon.

 Delay increases slowly as input bits increase.

 References
1)IETE JOURNAL OF RESEARCH , vol 55, nov - dec 2009,page no.285.

2)H S DHILON and A MITRA , a reduced –bit multiplication algorithm for digital
arthemetic , International Journal of Computational & Mathematical sciences,2 dec ,
2009.

3)Xilinx University program , basic FPGA architecture,

pp.2-46.

4)V A PEDRONI , circuit design with VHDL,PP.4.

5)M C HANUMANTHRAJU , a high speed block convolution using Ancient Indian Vedic
Mathematics.

        
 AUTHORS
Ramesh Pushpangadan  is an Assistant Professor in the Department of ECE, College of
Engineering Munnar . He is currently pursuing his PhD from Indian Institute of Technology
Mumbai. His areas of interests are VLSI design and renewable energy. 

Vineeth Sukumaran received his B.Tech in Electronics and Communication Engineering

from College of Engineering Munnar in 2009. He is currently an employee in State Bank of
India. His areas of interests include VLSI design and digital communication theory.

Rino Innocent received his B.Tech in Electronics and Communication Engineering from

College of Engineering Munnar in 2009. He is currently working as a communication engineer
in a private firm. His areas of interests include digital systems design and power electronics.

Dinesh Sasikumar received his B.Tech in Electronics and Communication Engineering from

College of Engineering Munnar in 2009. He is currently a Base Transceivers Station and
Microwave commissioning engineer at Calliper Telecom services. His areas of interests
include communication systems and signal processing.
QUERIES