Low Power Design Techniques

Low Power Design with nanoWatt XLP
Authors: Stu Chandler, Pr. TTE

Brant Ivey, AE
V1.20 April 2010

Objectives
When you finish this class you will be able to:

Define low power, its various modes, and how
to manage them.
Differentiate nanoWatt, nanoWatt XLP
Technology, Deep Sleep and other low power
features.
Analyze and design a system to consume the
least amount of power power possible.
Identify and choose the best nanoWatt
enabled PIC® for your application.
© 2010 Microchip Technology Incorporated. All Rights Reserved. PWR0110 Slide 2 of 98
Agenda
Defining Low Power

Power Budgeting & Planning
System Considerations
nanoWatt XLP Technology
Deep Sleep
Summary & References

Defining Low Power
Low Power Trends
Your customers demand low power!

Fast growing battery applications demand longer life
Green Initiatives: 1-Watt, Half-Watt
Energy Harvesting
Metering Consumer Medical Safety & Security

Application Requirements
Longer battery life ← Most critical requirement

Requirements dependent on usage scenario
Frequent wake-up
Long periods of inactivity
Increased feature integration
LCD ← Displays Pricing
Wireless ← Automatic Pricing Updates
Touch ← Options
USB
Increased robustness & reliability
Smaller form factor
Reduced heat dissipation
© 2010 Microchip Technology Incorporated. All Rights Reserved. eXtreme Low Power
PWR0110 Slide 6 of 98
Defining Low Power
Useful Relationships
Watt’s Law:
Power(Watts ) V (volts) I (amperes)
Joule’s Law:
Energy (Joules) V (volts) I (amperes)t(sec)
Charge:
q(coulombs)  I (amperes)t(sec)
Definition
Charge (ampereseconds) is the current used in a given period of
time. This is useful in calculating the power of each phase of an
application, or the total capacity of a battery.

Defining Low Power
Power Modes
There are several power modes in

microprocessor applications:
Dynamic (also called Active)
System clocks are on and operational
Parasitic, Clock, Peripheral, Core, I/O power
Static
System clocks off
Parasitic & I/O power
Average
Integral of the power used in one complete cycle of
the application

Defining Low Power
Dynamic Power
dynamic dynamic
Power (μA*V)
…..
wake-up
static
Time (μs)
Definition
Dynamic (Active) Power is the power consumed while the
application is active and executing tasks. This power is dominated by
CMOS switching currents which are a function of execution frequency
and voltage. Additional active power is consumed by peripherals and the
I/O pins.

Defining Low Power
Contributing Elements of Dynamic Power
CMOS transistor switching losses VDD

Both are temporarily on during
transition
Faster switching = more on time =
more leakage
input output
Gate capacitance
Load adds capacitance (CL)
Parasitic capacitance (CP) is
always present at ~5-10pF CP+CL
Supply Voltage
Lower voltage means lower
power consumption

Defining Low Power
Contributing Elements of Dynamic Power
Capacitance (C) is affected by

I C dV
Chip design
Peripheral selection
dt
Voltage (V) is affected by
Component selection P VI VC dV
dt
Frequency (f) is affected by
System Clock For constant V:
Code Efficiency
Power profile P CV 2 f
Application needs

Defining Low Power
Static Power
dynamic dynamic
Power (μA*V)
…..
wake-up
static
Time (μs)
Definition
Static Power is the power consumed while the application is on but
not active (i.e. system clock is off). This power dissipation comes from
transistor leakage inherent in CMOS processes, real-time clocks
necessary for time keeping which run during sleep, system voltage
supervisors, watch-dog timer circuits, I/O leakage and similar sources.

Defining Low Power
Contributing Elements of Static Power
VGATE
VSOURCE gate
VDRAIN
Gate-junction tunneling
source drain
Sub-threshold Leakage
Drain to substrate
leakage
Leakage is affected by:

Process geometry – smaller transistors mean higher leakage
Voltage – lower voltages mean lower leakage
Temperature – higher temperatures dramatically increase leakage
Smaller transistors increase static power BUT this can be offset by LOWER
DYNAMIC power since they can operate at a lower voltage.
Low power design is a series of tradeoffs at the design and application levels.

Defining Low Power
Average Power
1
Pavg   (Vactive  Iactive  tactive )  (Vstatic  Istatic  tstatic)
tcycle
dynamic dynamic
Power (μA*V)
…..
PAVG wake-up
static
Time (μs)
Definition
Average Power is the power consumed across one entire cycle

when operating in both static and active operation states over time.
The average power includes the amount of time spent in each state as
well as the transition time required to switch between active and static
modes.
Defining Low Power
Measuring Power Consumption
Multimeter Vdd
Measures RMS current
Typically accurate down to 20nA-100nA 3.3V device
under test
Oscilloscope with shunt resistor on V DD

Measures and displays power profile Rshunt
Vdd
Rshunt value must be carefully chosen
10Ω-100Ω
Too large Rshunt may cause BOR 3.3V device
under test
VDD Capacitor Discharge Vdd

10µF
Measure I=C(∆V/ ∆t) discharge rate
3.3V
Useful for very low current device
under test
measurement

Lowering Active Current
Execution Time x Active Current x Voltage
Choose device to minimize execution time
Choose device with lowest current
Can system voltage be lowered?
Can power supply be run on a single battery cell?
Extend the idle time

Choose device with long sleep times to minimize wake up cycles
Choose device with low sleep currents
Choose system elements carefully

Disable unused peripherals
Sensors and signal chain components
Choose efficient low dropout voltage regulators
Choose appropriate battery
© 2010 Microchip Technology Incorporated. All Rights Reserved. eXtreme Low Power
PWR0110 Slide 16 of 98
Operating Mode Summary
RUN [active power]
Core & Peripherals system clock speed
Typical current of 50-360µA/MHz (3V, 25°C)
LP INTRC (31kHz) as low as 8µA (1.8V, 25°C, PIC24F04KA201)
DOZE (some devices) [active power]

Core significantly slower than peripherals, peripherals full speed
Typically 35%-75% of RUN current
IDLE (some devices) [active power]

Increasing Battery
Core OFF, peripherals ON

Typically 25% of RUN current
SLEEP [static power]

Typically 100nA (3V, 25°C)
85°C specification as low as 1.35μA (1.8V, 85°C,PIC24F04KA201)
DEEP SLEEP (some devices) [static power]

SRAM, VREG, VBOR, RTCC off
Life
Typically 35nA (3V, 25°C)

Analyzing an Application
Break the application into phases
Calculate the current used in those phases
Determine how much time must be spent in each phase
Calculate the power consumed by each phase
Calculate the average power of the entire application

Can it be lowered by spending less time in active mode?
Can voltage, clock source or lower power modes be
changed in any of the phases?
Identify the worst cases and revisit

Can different mode combinations be used?
Plot the power profile
Build, measure, and confirm the power profile

Analyzing an Application
Break the
application into
SCHEDULE
phases
Wake-Up, Transition Sources,
Loop Control, Mode & Clock
control and switching
ACQUIRE
PROCESS
OUTPUT

Typical Application Block Diagram
1. Read Sensors
3.3V
2. Write to E2
3. Write to USART
4. Wait for 10s (with RTCC)
Potentiometer 5. Repeat
Analog
Temp
Sensor
MCP9700 S2 I2C
INT0 SSP Serial E2
INT1 24AA256
S3
ADC
POSC
8Mhz
PIC24F
8 MHz
FRC
CORE
500 kHz
LPRC
RS232 to
SOSC USART USB Bridge
PIC18F14K50
32kHz T1OSC
RTCC

Power Profile
Minimize the areas under the curve
Power (μA*V)
Run Run
B B
…
Run Run
A A
Idle wake-up
NOT TO SCALE
Time
Run A – Sample temperature sensor (800µs)

Run B – Write to EEPROM (5ms)
Loop/Sleep/Idle/Deep Sleep for (10s)
Run clock can be changed dynamically
Operating voltage can also be changed dynamically
nanoWatt XLP Battery Life Estimator
Select Device & Parameters
New device data supplied with new revisions,
or you can create data files yourself.
For example: “PIC18LFxxJ11.csv”
Select Battery
New battery data can be added by
modifying “CustomBattery.csv”
Enter power profile modes
Review & Save

Instruction Efficiency
How many instruction cycles does it take to

perform a task?
Not all architectures are equally efficient
Evaluate benchmarks such as EEMBC’s CoreMark
suite for first pass analysis
Build and benchmark with simulator
Build and measure hardware
Development tools such as 16-Bit nanoWatt XLP
Evaluation board are designed for this type of analysis
Don’t stop at the front page of the data sheet
μA/MHz does not tell the whole story!
Instruction Efficiency Example
Except for multiplication most PIC16 and PIC18 instructions are equivalent
PIC18 has a single cycle hardware 8x8 multiplier.
PIC16 emulates multiplication at instruction level
How much energy does it take to perform an 8x8 multiply?
PIC16LF727 @1MHz @1.8V @25°C

80μA/MHz
Instruction cycle @1MHz = 4μs #include <htc.h>
62 instruction cycles = 248μs unsigned char A,B;
80μA * 1.8V = 144μW unsigned int C;
144μW * 248μs = 35.7nJ void main (void)

{
A = 2;
PIC18LF46J11 @1MHz @2.0V @25°C B = 4;

C = (unsigned int)A * (unsigned int)B;
275μA/MHz }
Instruction cycle @1MHz = 4μs
5 instruction cycles = 20μs
2.0V * 275μA = 550μW
550μW * 20μs = 11nJ

Instruction Efficiency
Benchmark execution time for your application using compiler
and a cycle-accurate simulator with stop watch features
Normalized Execution Time
6
5 PIC MCU
4 Competitor
3
2
1
0
Note: Industry Standard Benchmark Algorithms

Competitor 16-bit MCU family at 16 MIPS - Speed & Size trade off = 5
PIC24F family at 16 MIPS using MPLAB® C Compiler for PIC24F with Optimization level O3

Battery Selection
Battery chemistry is critical
Lithium coin cells
very low self discharge for good shelf life
very low max current limits
high internal resistance. High peak currents will drop voltage and
hurt lifetimes.
New! Lithium AAA cells
Useful range matches the voltage range of most microcontrollers
Low internal resistance. Support high peak currents
Low self discharge – long shelf life
Alkaline batteries
high capacities and high current drain supported
capacity drops as the current output rises
Secondary cells (rechargeable NiCd, NiMH etc.)
high self discharge
require frequent recharging even if application is very low power.

60°C Battery Specification
Batteries of most chemistries are specified
up to 60°C
nanoWatt XLP devices now include a 60°C
specification point in the data

Managing External Circuit Power
All circuits are always powered
Power management relies on individual standby modes
3.3V
Analog
Temp
Sensor S2
MCP9700 I2C
Serial E2
24AA256
S3
8Mhz
High
Current
Output
32kHz

Managing External Circuit Power
PIC® MCU can provide power directly from I/O pins as needed
FETs can be used for high current circuits or voltage differences
3.3V
Analog
Temp
Sensor S2
MCP9700 I2C
GPIO GPIO Serial E2
24AA256
S3
8Mhz GPIO
High
Current
Output
32kHz

Reduce Voltage
3.30V
15μA 3mA 11mA
2.50V
2mA
8μA
32kHz
Reducing system voltage impacts dynamic & static current

Use lowest output regulators for performance required
Consider reducing Vdd with programmable voltage regulators while
in sleep or idle modes

Power Supply
Some nanoWatt XLP devices are based

(Regulator Enabled)
on low voltage process:

Core requires 2.5V or 1.8V
Connection to 3.3V power supply or I/O
(no Regulator) logic requires low dropout voltage regulator
(LDO)
Some F devices include internal LDO
LF devices usually do not
Choices are:
Use F device with internal LDO
Design for 2.5V (or 1.8V) I/O & power supply
Use multiple power supplies

Managing Vddcore
Carefully choosing the system low drop out regulator
may result in lower static current
PIC18F46J11 LDO quiescent current ~3μA
MCP1702 external LDO quiescent current ~2μA
For low current applications, external LDO may be
better choice
MCP1702 Linear Regulator

Specifications:
2.0 µA typical quiescent current
2.7V-13.2V input voltage
Low Dropout Voltage: 650mV (typ) @250mA
0.2%/V Line regulation 0.2%/V
Short Circuit & Thermal Shutdown protection

Minimize RAM access
Reading RAM requires more power than reading FLASH
Standard_Routine: // compiles to 3 instructions

while(!_T1IF) i++;
19.1 mA
The routine reads _T1IF (Timer 1 interrupt flag) and writes i every
time through the loop.
At 32MHz:
Loop time is 187ns
Measured average current is 19.1mA while in this loop
It will read & write RAM twice every 187ns
Does the application really need this response time?

Minimize RAM access
Low_Power_Routine: // compiles to 8 instructions
while(!_T1IF){
i++;
Nop();
Nop();
Nop();
Nop();
Nop();}
16.4 mA
At 32MHz loop time is 500ns
reads & writes RAM twice every 500ns
Note improvement of 2.5mA
Reduced power by ~13% by adding five NOPS!

I/O Recommendations
Use internal pull-ups for buttons

Internal pull-ups can be disabled after detection
Use software de-bouncing
Trade off dynamic processor current for static
leakage of RC de-bounce network
Use high power LEDs
Drive at much lower than rated current
PWM instead of direct drive
High power LEDs driven at low current are still visible
25mA rated LED still visible down to 100uA

I/O Recommendations
Use highest resistance pull-ups possible

Poll resistor ladders
Power through I/O pins and turn on only when
necessary
Use low leakage caps
Tantalum are typically high leakage
Can be as high as 1µA @10µF
Ceramics are lowest leakage
~20nA @10µF
Use bypass caps sparingly Equivalent capacitor model
Each one adds leakage

Keep traces short
Short traces mean low impedance

Eliminate Floating I/O
Typical Case Worst Case
1 Floating Pin 35 µA 0.5 mA

2 Floating Pins 65 µA 1 mA
10 Floating Pins 305 µA 5 mA
Floating CMOS pins

Float to VDD/2
High leakage currents
External signals can be induced on floating pins
Eliminate floating input pins
Set unused I/O pins to outputs
Drive them low

Reducing Wake-Up Time
Crystals:
Are held off for 1024 cycles for reliable start up
Ensures that crystal is up and stable
Extremely important feature for reliability across variety of
temperature and start up conditions
At least 32ms @32kHz, 64μs @ 8MHz
Can be significantly longer – under certain environmental conditions
can be up to 1s
Internal RC (INTRC) oscillators:

Certain ones can wake up within 1μs-5μs for INTRC
Two-speed start-up Mode

Wake-up with INTRC
Certain devices feature INTRC accuracy of 0.25%
Switch to crystal when ready if PPM accuracy is required
Disable unused peripherals

All on-chip peripherals have some control bits or PMD bits to
disable
Optimizing compiler code
Experiment with combinations of speed, code size and RAM
usage optimizations
Look for fastest execution at lowest code size with minimal RAM
access
Benchmark execution time on your algorithm
For example:
32MHz on different platforms may not equal same execution time
Over 90% of PIC MCU instructions execute in a single-cycle
Device simulator is available free with MPLAB® IDE

Consider using SPI peripherals instead of I2C
Less sensitive to pull up values
Faster
Use less dynamic power
Reduce time in service loop
Many peripherals such as EEPROM come in both types

Low Power Analog & Interface
Architectural
Dominance
PIC® MCU
Field Analog & Interface

Programmability
Digital control over
Proprietary FLASH cell analog domain
Microchip uniquely combines these three core

competencies to serve the embedded control market.

Microchip Analog & Interface
Advantage
Flexibility:
Our knowledge of Non-Volatile Memory (NVM)
makes analog easier to manufacture and
offers flexibility
Using both internal and external fabs allows
flexibility and safety for our customers
Analog for digital systems:
Easy to use development tools
Robust MOSFET drivers, stable op amps
Standard digital serial interfaces
Advantage
Low Power/Low Voltage
Op Amps with lowest power for a given bandwidth
600 nA/1.4V/10 kHz bandwidth Op Amps
1.8V charge pumps and comparators
Robust
MOSFET drivers lead the industry in latch-up
immunity and stability
Integration Innovation
Switcher + LDO, LDO + Supervisor, etc.
MCP6S PGA Family integrates MUX, Resistive Ladder,
Gain Switches, High-Performance Amplifier, SPI
Interface into one device

Advantage
Space savings
Highest resolution 18-bit ADC in SOT-23 package
Op amps, comparators, resets and LDOs in SC70, ADCs,
temperature sensors in 5 lead SOT-23
CAN and IrDA® standard protocol stack embedded in an
18-pin packages
Accuracy
Offset trimmed after packaging using non-volatile
memory
Innovation
Low pin-count embedded IrDA® standard stack,
Fan Sense technology
Select Mode™ operation

Proprietary Low Power
Enabling Technologies
1 µA Band gap References
Low Power CMOS - Enables low Simplified Designs
power references and voltage
Process - - Proprietary
regulators
Lower power than competing designs reduce circuit
processes complexity giving more
performance for less power
The Low Power

Analog Solution
Non-Volatile Trim Understanding of
- Accuracy achieved Customer Needs
through after-package trimming, Temperature Stable High - Only necessary
not complex, power consuming features are included,
Value Poly Resistors
circuitry unnecessary power consuming
- High resistance in small space
needed for low power features are left out
consumption, difficult to
manufacture

Low Power Analog & Interface
THERMAL POWER
MIXED SIGNAL INTERFACE
MANAGEMENT MANAGEMENT
Temperature Delta-Sigma
Linear Regulators CAN/LIN
Sensors A/D Converters
Brushless DC Switching SAR A/D

Fan Speed Controllers Serial Peripherals
Fan Fault Detectors Regulators/Controllers Converters
Charge Pump Energy

Measurement ICs Ethernet Controller
DC/DC Converters
LINEAR
Voltage Dual Slope / Display
RF and Infrared
References A/D Converters
Single Supply
CMOS Op Amps CPU/System
D/A Converters
Supervisors
SAFETY AND
Comparators
Voltage Detectors V/F and F/V SECURITY
Converters
Programmable/
Power MOSFET Smoke Detector ICs
Selectable Gain Amps Digital Potentiometers
Drivers
Piezoelectric
Battery Management Horn Drivers
PWM Controller

Low Power Solution
Using a Real-Time Clock
Vcc
Crystal X1 Vcc
32.768 kHz ___ Or LDO
X2 IRQ/CLK Vcc
Vbat VBAT SCL SCL

SDA
Vss SDA
+3V
Typical MCP79410
MCU
MCU programs alarm wakeup times into RTCC

RTCC powers down MCU for super low power system
Backup battery maintains timekeeping & SRAM when VCC OFF
Stand-Alone
I2C™ Real-Time Clock/Calendar
1.8V minimum operating voltage

1.3V timekeeping & SRAM retention from VBAT (700 nA)
Automatic battery switchover
Programmable alarm output (VCC or VBAT)
1 Kbits EEPROM plus 64-bit Unique ID (protected EE)
64 bytes of SRAM
Vcc
Digital Trimming Crystal
32.768 kHz Alarm Output R Time S
Resolution: 1 ppm T
C
Stamp/ R
A
OR
1 Hz to 32 kHz
C Alarms M
Range: +127 ppm
Timestamp VBAT
Switchover
I2C Serial Interface I2C I2C Bus
EEPROM ID
SPI & UNI/O® (Future)

nanoWatt XLP Technology
nanoWatt XLP
Useful Power Management Features
Flexibility
Multiple clocking options
Dynamically configurable speeds and sources
Peripherals equipped for low power modes
Peripheral & wakeup source configuration options for low
power modes
Low power oscillators
Allow timekeeping with WDT, Timer1 or RTCC without
breaking the power budget
Low digital input leakage
Typically < 50nA, some as low as 5nA
Minimizes static power
Fast wake-up times
Minimizes time lost in wake-up transition zone

nanoWatt XLP
nanoWatt Technology (2003)
nanoWatt Technology
Introduced in 2003
Standard for all new Microchip MCUs since 2003
Affected by chip design, manufacturing processes,
peripheral & clock mix, and testing capabilities
Defined as:
Standby (Sleep mode) power < 1μW
@3V Ipd < 333nA (PIC24H)
@2V Ipd < 500nA (PIC16,PIC18,PIC24F)
Definition
nanoWatt Technology
Microchip proprietary suite of design techniques used to design
microprocessors capable of power consumption below 1μW in
standby mode (Ipd).

nanoWatt XLP
nanoWatt Technology (2003)
IDLE mode
CPU OFF, Peripherals ON
On chip, high speed internal RC oscillator (INTRC) with PLL and
programmable post-scaler. This enabled:
Rapid startup in 1µs-5µs
Two speed start up (start on INTRC, then switch to crystal if needed)
Dynamically selectable clock speeds
Extended WDT time out interval
Maximum time out increased from 18ms to 131s
Low power redesign for Timer 1 (TMR1) and the 32kHZ secondary
oscillator (SOSC)
Low power software controllable BOR
Standard BOR was redesigned to consume less power
Software can turn it off when not needed, e.g. during sleep

nanoWatt XLP
nanoWatt XLP Technology (2009)
nanoWatt XLP (eXtreme Low Power)
Introduced in 2009 as the next generation of nanoWatt
Low leakage gate design employed throughout
Design and manufacturing processes fined tuned for low power
Specialized low power peripherals introduced
Requirements Best specifications
Defined as: achieved to date
Sleep: 100nA or less 13nA @1.8V

Real-Time Clock Calendar (RTCC): 800nA or less 500nA @1.8V
Watchdog Timer (WDT): 800nA or less 200nA @2.0V
Definition
nanoWatt XLP (eXtreme Low Power) Technology
Microchip proprietary technology used to design microprocessors with
power consumption below 100nA in standby mode, 800nA running
RTCC and 800nA running WDT.

nanoWatt XLP
nanoWatt XLP Technology (2009)
Introducing specialized power management features:

Deep Sleep (DS)
Deep Sleep Brown Out Reset (DSBOR)
Deep Sleep Watch Dog Timer (DSWDT)
Low input leakage current
60°C specifications for convenience when
specifying battery applications
Example of Battery Life Improvement (25°C)

Battery Type: Coin Cell (CR2032)
1ms RUN at 1MHz, then Deep Sleep with RTCC enabled
PIC24FxxKA with nanoWatt XLP - Up to 20 years

nanoWatt XLP
Devices Include Dual Brown-Out Resets
Brown-Out Reset (BOR)

Standard nanoWatt BOR
Some devices call this LPBOR
Configurable to four voltage levels
Typical power consumption is ~5µA
Deep Sleep BOR (DSBOR)

Available in addition to BOR on devices with
Deep Sleep mode
Fixed trip point ~1.8V
Some devices as low as 5nA

nanoWatt XLP
Devices Include Dual Watch Dog Timers
Watch Dog Timer (WDT)

Standard nanoWatt WDT
IΔWDT down to 500nA
Time out period range: 1ms–131s
Deep Sleep WDT (DSWDT)

Available in addition to WDT on devices with
Deep Sleep mode
Useful for applications that are inactive for long
periods of time
DSWDT stays alive in Deep Sleep mode
IΔWDT down to 370nA
Time-out period range: 2.1ms-25.1 days

nanoWatt XLP
Ultra Low-Power Wake-Up (ULPWU) Module
Standard module on most devices
Internal current source with external capacitor allows very long
term, low power wakeup
75nA-160nA operating current
Comparable time out to DSWDT but up to 80% less current
Doesn’t float and draw excessive current like a standard I/O pin
Wake-up time varies with temperature & humidity

nanoWatt XLP
Peripheral Module Control
Peripheral Enable Bits
Located in each peripheral’s control SFRs
Disables/enables functionality to that peripheral
Control registers are still available for reading & writing
Example: AD1CON1<ADON>
Some device families have additional Peripheral Module

Disable (PMD) control bits
Located in PMD registers
Disables all clock sources to peripheral
Removes power from associated control and status registers
Example: PMD1<ADC1MD>

nanoWatt XLP
Operating Modes – A Closer Look
PIC16 PIC18 PIC24

RUN
  
All systems running
DOZE

CPU slower than peripherals
IDLE
 
CPU off, Peripherals on
SLEEP
  
System clock off
DEEP SLEEP
 
RAM off, Vreg off

nanoWatt XLP
PIC16 XLP Clock Options
Primary
OSC RUN
CPU &
4X PLL
Peripherals
Secondary
OSC
Internal SLEEP
RC POSTSCALER
(31kHz to
16MHz
...
16MHz)
500kHz
31kHz
Optional Peripheral
Clock Source
WDT, PWRT
& FSCM

nanoWatt XLP
SLEEP
Primary Peripherals
OSC
4X PLL
Secondary
OSC RUN
Internal CPU
RC POSTSCALER
IDLE
(31kHz to
16MHz
...
16MHz)
500kHz
31kHz
Optional Peripheral
Clock Source
WDT, PWRT
& FSCM

nanoWatt XLP
Ext. Clock Output SLEEP
Primary
OSC Peripherals
4X PLL
Secondary
OSC DOZE
RUN
POSTSCALER
Internal
RC POSTSCALER
8MHz (1.95kHz to CPU

...
500kHz
8MHz) IDLE
31kHz
Optional Peripheral
Clock Source
WDT, PWRT
& FSCM

nanoWatt XLP
Run Mode
All resources
VDD VREG VDDCORE CPU active
POSC Post-Scaler RAM
Dynamically
HS
reconfigurable
system clock
INTRC Flash
LP
INTRC Peripherals
BOR
T1OSC Analog
SOSC
INT0
WDT
RTCC
Timer1

nanoWatt XLP
Clock Switching
VDD VREG VDDCORE CPU

Multiple clock
sources
Can switch
dynamically
HS
Flash
INTRC
LP
INTRC Peripherals Affects all parts
BOR
of the chip
T1OSC Analog
SOSC
INT0
WDT
RTCC
Timer1

nanoWatt XLP
Clock Switching
Slowing the clock can save more power than
Idle/Doze modes
Slower clock affects all areas of the chip
Two speed startup
Startup on INTRC in 1μs-5μs
Switch to crystal mode if needed
Run on INTRC while waiting on PLL to lock
Useful when waiting on external events or slow
peripherals such as ADC, comparators,
communication ports, etc.

nanoWatt XLP
Doze Mode

CPU &
Memory run at
POSC Post-Scaler RAM slower clock
HS
INTRC
Flash Peripherals
LP
still on full
speed system
INTRC Peripherals
BOR
T1OSC
SOSC
Analog clock
INT0
WDT 35-75% of Run

RTCC
Timer1
Mode current

nanoWatt XLP
Idle Mode

CPU is turned
off
Peripherals
HS
INTRC
Flash
remain on
LP 25% of Run
INTRC Peripherals
BOR Mode current

T1OSC Analog
SOSC
INT0
WDT
RTCC
Timer1

nanoWatt XLP
Idle & Doze Modes
When should Idle or Doze modes be used?

Replace while(!Interrupt) loops
Slow down while waiting for the peripheral or an interrupt
When short power-down times requiring very fast wakeup are needed
e.g. wakeup less than ~1 instruction cycle
Transition time is minimal
During DMA transfers
When application must be continuously sampling or communicating

nanoWatt XLP
Sleep Mode
50-100nA without
VDD VREG VDDCORE CPU regulator
3-5µA with internal
POSC Post-Scaler RAM regulator
HS
System clocks,
INTRC
Flash
CPU off
LP
Peripherals
RAM remains
INTRC
BOR
powered
T1OSC Analog Regulators remain
SOSC
INT0 powered
WDT
Certain Peripherals
RTCC
can be configured
Timer1
to run in sleep

nanoWatt XLP
Deep Sleep Mode
VDD VREG VDDCORE CPU <50nA

RAM is powered down
DSGPR (2)
Regulators are
powered down
HS
Flash Certain peripherals
INTRC
continue to run in
LP Deep Sleep
INTRC Peripherals
DSBOR
BOR
DSBOR
DSWDT
T1OSC Analog
SOSC RTCC
INT0
INT0 INT0
WDT
DSWDT
RTCC
RTCC
Timer1

nanoWatt XLP
Deep Sleep Mode
Core power is removed
This causes loss of RAM, SFRs and Program Counter
Two DSGPR registers are provided to retain variables
during Deep Sleep
Wake-up time includes time for voltage regulator to
power back up when (using internal Vreg)
Wakeup causes Power On Reset (POR)
Standard Sleep
resumes execution where it went to sleep
Deep Sleep does not
wakes up with cleared program counter
I/O states are maintained
nanoWatt XLP
Mode Summary
Modes Active Clocks Active Peripherals Wakeup Typical Typical Usage
Sources Current
RUN All All
All All All ~50% of Run Applications with high-speed

DOZE Software wakeup Current peripherals requiring low
CPU use
Peripheral Clocks All All ~25% of Run Anytime device is waiting for
Timer1 Current an event
IDLE Secondary OSC
INTRC
LPRC
ADC RC
Timer1 RTCC Timer1 All 50-100 nA base Most low-power apps
Secondary OSC WDT INTx
SLEEP INTRC BOR ADC 3-5 uA with
LPRC HLVD CVREF Internal
ADC RC Comparators Regulator
UART-RX
Secondary OSC RTCC RTCC < 50 nA base Long-life battery based
LPRC DSWDT DSWDT applications, applications
DEEP DSBOR DSBOR Peripherals add with long sleep times
SLEEP INT0 INT0 incremental
MCLR current
ULPWU

nanoWatt XLP
Power Consumption Comparisons
PIC24FJ64GA104
PIC24FJ64GB004
PIC24F16KA102
PIC24F04KA201
PIC18LF14K50
PIC18LF46K20
PIC18LF14K22
PIC18LF46J11
PIC18LF46J50
PIC16LF1827
PIC16LF1937
PIC16LF727
Deep Sleep (nA) 13 15 20 20 20 20
Sleep (nA) 20 60 20 34 24 54 60 100 25 25 200 200
WDT (nA) 500 500 500 460 450 820 780 600 400 400 200 200
32kHz SOSC/RTCC (nA) 600 600 600 650 790 850 830 600 500 500 500 500
1 MHz Run (μA) 80 93 80 131 125 275 275 131 195 195 250 250
Minimum Vdd (V) 1.8 1.8 1.8 1.8 1.8 2.0 2.0 1.8 1.8 1.8 2.0 2.0
Current specifications are typical (TYP) values at minimum V dd

Deep Sleep
Deep Sleep
What is Deep Sleep (DS)?
Final frontier in power management

Turns off power to:
Core, Peripherals, SRAM & Voltage
Regulator
Lowest power mode:
As low as 13 nA
RTCC during DS as low as 500 nA
I/O pins remain powered and retain
their state through Deep Sleep
Select peripherals still operate and can
wake up from Deep Sleep
Deep Sleep
How is it different than Sleep?
Can consume 90% less power than Sleep

SRAM disabled Power Consumption
Registers NOT retained during DS
Special registers for saving context
Two registers retain data during DS
FLASH or EEPROM can also be used
Internal low drop-out voltage regulator
(LDO) shuts down
Not all devices have LDO Deep
Active Sleep
Sleep
DS wake-up causes a Power-On Reset
Execution resumes at the RESET vector
SFRs reset to default values
RCON<DPSLP> bit set by hardware

Deep Sleep
Sleep vs. Deep Sleep Comparison
Low Power Mode SLEEP DEEP SLEEP
Definition Core powered off, Core, Peripherals, SRAM &
Some peripherals can Voltage regulator powered
operate, RAM retained off
Wake-Up Sources RTCC DS RTCC
Power
Watch-Dog Timer DS Watch-Dog Timer
Brown-out Reset DS Brown-out Reset Profile Run
Interrupt Pins INT0
ULPWU ULPWU
Power
Power-On Reset Power-On Reset
Reset Pin (MCLR) Reset Pin (MCLR) Sleep
Peripherals
UART (RX) Deep Sleep
Wake Up Time Shorter (~1µ-5µS typ) Longer (same as POR)
Operation Time
Pin State Maintained Maintained
RAM State Maintained Two words maintained

Deep Sleep
When is DS effective?
When the application:

Is inactive for high percentage of the
application cycle
Typically more than 1s
Is inactive for long periods of time
Requires accurate timekeeping with minimal
current
Runs at extreme temperatures
Requires small group of active peripherals

Deep Sleep
When is DS effective?
In high temperature applications:
25ºC
870nA
Current (nA) 60ºC
430nA
25nA 20nA
Sleep Deep Sleep
PIC24F16KA102
25ºC specifications - Typ Ipd @ 1.8V
60ºC specifications - Max Ipd @ 1.8V

Deep Sleep
What operates during DS?
RTCC
Continues to keep time
RTCC pin can optionally output every second
I/O Pins
Maintain State
Special Deep Sleep registers retain values:
DSGPR0 – DS General Purpose Register 0
DSGPR1 – DS General Purpose Register 1
RTCC – Real Time Clock Calendar
DSBOR (Deep Sleep Brown Out Reset)
Monitors VDD during DS
DSWDT (Deep Sleep Watch Dog Timer)
Deep Sleep
Which Devices Support DS?
PIC MCU Family Min. Family Flash Pins Sleep DS WDT TMR1 1MHz
Vdd Members kB (nA) (nA) DSWDT RTCC Run
(nA) (nA) (µA)
PIC18F46J11 2.0 6 16-64 28-44 54 13 820 850 275
PIC18F46J50 2.0 6 16-64 28-44 60 15 780 830 275
PIC24F04KA201 1.8 2 4 14-20 25 20 400 500 195
PIC24F16KA102 1.8 4 8-16 20-28 25 20 400 500 195
PIC24FJ64GA104 2.0 4 32-64 28-44 200 20 200 500 250
PIC24FJ64GB004 2.0 4 32-64 28-44 200 20 200 500 250
Six families - twenty-six devices - and growing

Deep Sleep
Break-Even Time
Break-Even Time
DS shuts off the core, SRAM & voltage regulator power
At DS wake-up:
Voltage regulator powers up
POR cycle completes
Clock starts up
Context is restored
Wake-Up time becomes dominant
For short sleep times, standard sleep mode may be
better choice
Definition
Break-Even Time
The point at which Deep Sleep uses less power than Sleep

Deep Sleep
Contributing Elements of Wake-Up Time
dynamic
…..
Power
Wake-Up Time
….. static
Vreg start up time Time
typically 10μs
Required when using devices with internal LDO
Power Up Time
Typically 72ms
Clock start up time
Crystals can be many ms
Resonators can start up within 100μs-200μs
Two speed start up
Fast RC OSC starts up within 1μs-5μs at % accuracy
Operate application while waiting for crystal
Switch to crystal at PPM accuracy when crystal is ready
Deep Sleep
Break-Even Time
Power used during Sleep
 
t I  V
 
P
sleep  sleep sleep  supply
Power used during DS + init + POR

     
P   t I    t I    t I 
V
DS  DS DS   init init   POR POR  supply
At Break-Even time, the amount of power used is the

same for either Sleep or Deep Sleep
Choose the mode that will use the least power:
At some point out in time the DS + POR + INIT power will be
less than the Sleep power
If the application can sleep for that time, then choose DS
If the application cannot sleep for that time, then Sleep is the
better choice
Deep Sleep
When to use Deep Sleep?
PIC18F46J11
on-chip LDO ON
3.9μA SLEEP
3.1μA
Average Current
Use DS when time PIC18F46J11

Tbreak-even on-chip LDO OFF
between wake-up events
DEEP SLEEP
is longer than the time it
takes to wake from DS
and turn on the LDO
PIC18LF46J11
PIC18F46J11 NO on-chip LDO SLEEP
on-chip LDO off
420nA
DEEP SLEEP 70nA
54nA 13nA
1s 10s 100s 1000s
Time between Wake-up Events

Deep Sleep
DS Control Registers
DS mode retains power to these registers:
DSCON
DS Control Register
DSWSRC
DS Wake-Up Source Registers
Track source of wake-up from DS
Register should be polled upon wake-up
DSGPR0 & DSGPR1
General Purpose Registers useful for saving context, status or state
information through DS
16-bits for PIC24
8-bits for PIC18

Deep Sleep
DS Control Register
DSCON: Deep Sleep Control Register (PIC24F16KA102)
HS,
R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/C-0
DSEN - - - - - - - - - - - - - DSBOR REL.
15 0
<15> DSEN: Deep Sleep Enable Bit

1 = enters Deep Sleep on PWRSAV #0
0 = enters Normal Sleep on PWRSAV #0
<14:2> Unimplemented: Read as ‘0’
<1> DSBOR: Deep Sleep BOR Event bit
1 = the DSBOR was active and a BOR event was detected during Deep Sleep
0 = the DSBOR was not active, or was active but did not detect a BOR event during DS
<0> RELEASE: I/O Pin State Release bit
1 = Upon waking from Deep Sleep, I/O pins maintain their states previous to DS entry
0 = release I/O pins from their states previous to DS entry and allow TRIS & LAT bits
to control their states

Deep Sleep
DSCON<RELEASE> Behavior
Upon POR (Power On Reset) or wake up from DS
I/O port TRIS & LAT bits are reset to default
OSCCON<SOSCEN> bit is cleared
Disables SOSC (Secondary Oscillator)
Has the effect of disabling RTCC
Core holds TRIS, LAT & SOSCEN control in state
they were in before entering DS mode
Core does this by setting DSCON<RELEASE>
Application must:
Re-configure TRIS, LAT, & SOSCEN
Clear DSCON<RELEASE>
Turns I/O and SOSC control back over to application
Restore RAM and context information
Deep Sleep
DS Wake Up Sources
DSWSRC: Deep Sleep Wake Up Source Register (PIC24F16KA102)
HS, HS, HS, HS, HS, HS,

U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0
- - - - - - - DSINT0 DSFLT - - DSWDT DSRTCC DSMCLR - DSPOR
15 0

<8> DSINT0: Interrupt on change bit
1 = interrupt on change was asserted during DS
0 = interrupt on change was not asserted during DS
<7> DSFLT: DS Fault detected bit
1 = a fault occurred during DS and some DS config settings may have been corrupted
0 = no fault was detected during DS
<4> DSWDT: DS watch dog timer time out bit
1 = the DS WDT timed out during DS
0 = the DS WDT did not time out during DS
<3> DSRTCC: DS Real Time Clock Calendar alarm bit
1 = the DSRTCC triggered an alarm during DS
0 = the DSRTCC did not trigger an alarm during DS
<2> DSMCLR: MCLR event bit
1 = the MCLR pin was active and asserted during DS
0 = the MCLR pin was not active or was active but not asserted during DS
<1> Unimplemented: Read as ‘0’
<0> DSPOR: Power On Reset bit
1 = the Vdd supply POR circuit was active and a POR event was detected
0 = the Vdd supply POR circuit was not active, or was active but did not detect a POR event

Deep Sleep
Deep Sleep Cycle
POR
Enable SOSC for RTCC

Configure TRIS & LAT
-- DS RESET ROUTINE --
Read DSWSRC & DSCON<DSBOR>
Wake-Up YES
Wake-Up Event
Restore DSGRP0 & DSGPR1

from DS?
Clear RCON<DPSLP>
NO Clear DSCON<RELEASE>
-- STANDARD RESET ROUTINE --
Application Code
Save context registers

Set DSCON<DSEN>
Enter Deep Sleep

Deep Sleep
Entering Deep Sleep
;--------------------------------------- entering Deep Sleep Mode PIC24F16KA102
1 _FDS(DSWDTEN_ON & DSBOREN_ON & RTCOSC_SOSC & DSWDTOSC_SOSC & DSWDTPS_DSWDTPSF)
; DSWDT & DSBOR are configured by the configuration bits (_FDS) and are not accessible at run time
; enable and configure DSWDT in configuration word FDS

; configure DSWDT clock in configuration word FDS
; enable DSBOREN in configuration word FDS
2 CALL ENABLE-RTCC ; configure and enable the RTCC and clock source
CALL SAVE-DSGPR0 ; save context into deep sleep GPR0

3 CALL SAVE-DSGPR1 ; save additional context into deep sleep GPR1
CALL SAVE-EEPROM ; save any context that won’t fit into DSGPRs into EEPROM or FLASH
BSET DSCON, #DSEN ; setting this bit means that sleep command will invoke Deep Sleep
4 PWRSAV #0 ; enter within one instruction cycle or the #DSEN bit will be cleared
1 Enable and configure DSWDT & DSBOREN in

configuration bits (if they will be used)
2 Enable and configure RTCC (if it will be used)
3 Save the context in DSGPR0 & DSGPR1 & EEPROM
4 Set the DSCON<DSEN> bit & invoke SLEEP mode
Deep Sleep
Wake-Up From Deep Sleep
DS maintains I/O pins and DS Registers

DS wake-up options
INT0 (Interrupt 0)
DSWDT (Deep Sleep Watchdog Timer)
RTCC Alarm
ULPWU (Ultra Low-Power Wake-Up)
Will also wake up from DS but with limitations

Master Clear pin (MCLR)
I/O pin states will not be retained because DSCON<RELEASE>
is immediately cleared
Power cycle
I/O pin states will not be retained
Deep Sleep registers will not be retained

Deep Sleep
Wake Up From Deep Sleep
;--------------------------------------- exiting Deep Sleep Mode PIC24F16KA102
IF RCON<DPSLP> = 1 ; are we at the reset vector because of wake-up due to Deep Sleep?
{
CALL RESTORE-DSGPR0 ; retrieve context from deep sleep GPR0
1 CALL RESTORE-DSGPR1 ; retrieve additional context from deep sleep GPR1
CALL RESTORE-EEPROM ; retrieve any context saved in EEPROM
CALL RESTORE-IO-PINS ; restore I/O pin configuration

2 CALL ENABLE-RTCC ; configure and enable the RTCC and clock source
BCLR RCON, #DSLP ; clear the DPSLP status bit

3 BCLR DSCON, #RELEASE ; clear the RELEASE bit and return control to the hardware
}
1 Restore the DSGPRx registers & context

2 Restore I/O pin configuration & re-enable and
configure RTCC (if it will be used)
3 Clear the DSLP & RELEASE bits and return
control to application
Deep Sleep
Wake Up by DSWDT
Deep Sleep Watchdog Timer (DSWDT)
Separate module from standard WDT
Two clock sources available

Secondary Oscillator (SOSC)
Can be used optionally as clock source
INTRC
Best choice for reliable system operation
Will wake up even if crystal has failed
No external components required
Sixteen time-out settings available:

2.1ms, 8.3ms, 33ms, 132ms, 528ms
2.1s, 8.5s, 34s, 135s
9 minutes, 36 minutes
2.4 hours, 9.6 hours, 38.5 hours
6.4 days, 25.1 days
Deep Sleep
Wake Up by RTCC Alarm
RTCC Alarm
Alarm resolution from seconds up
through days & years
Uses the same clock sources as DSWDT
Save power: avoid using two different clock
sources
Optionally output a seconds clock or
Alarm Pulse on RTCC Pin During Deep
Sleep
Provides a wake-up or alarm signal to
external devices

Deep Sleep
Wake Up by ULPWU
Ultra Low-Power Wake-Up

I/O pin output high
-
C1 charges
ULPWU enabled
DS entered
Small pull-down current

discharges C1
Voltage
500mV threshold reached

- device wakes up
Time
Summary & References
nanoWatt XLP
Extreme Low Power Microcontrollers
PIC MCU Family Min Family Flash Pins Sleep DS WDT TMR1 1MHz
.Vdd Members kB (nA) (nA) DSWDT RTCC Run
(nA) (nA) (µA)
PIC12LF1822 1.8 1 3.5 8 20 - 500 600 75
PIC16LF1827 1.8 5 3.5-7 18-28 20 - 500 600 80
PIC16LF1937 [LCD] 1.8 8 7-28 28-44 60 - 500 600 93
PIC16LF727 1.8 5 3.5-14 28-44 20 - 500 600 80
PIC18LF14K22 1.8 2 8-16 20 34 - 460 650 131
PIC18LF14K50 1.8 2 8-16 20 24 - 450 790 125
PIC18F46J11 2.0 6 16-64 28-44 54 13 820 850 275
PIC18F46J50 2.0 6 16-64 28-44 60 15 780 830 275
PIC18F46K20 1.8 8 8-64 28-44 100 - 600 600 131
PIC24F04KA201 1.8 2 4 14-20 25 20 400 500 195
PIC24F16KA102 1.8 4 8-16 20-28 25 20 400 500 195
PIC24FJ64GA104 2.0 4 32-64 28-44 200 20 200 500 250
PIC24FJ64GB004 2.0 4 32-64 28-44 200 20 200 500 250
XLP Development Tools
XLP 16-bit Development Board XLP 8-bit Development Board

20/28-pin Format PIM Format (8 to 80-pin devices)
USB to PC for Display LCD Display
Battery or Harvester Power Battery or Harvester Power
PICtail™ Connector PICtail Connector
EEPROM, Temp. Sensor, LED, EEPROM, Temp. Sensor, LED,
Potentiometer Potentiometer
<<100 nA Capability <<100 nA Capability
Available now for $59.99 Launching summer 2010
Summary
References
PIC24F Family Reference

Manual
Summary
XLP Home Page
www.microchip.com/xlp
Summary
What did we learn today?

System design considerations for low power application
The differences between nanoWatt & nanoWatt XLP
Technology
Advantages offered by Deep Sleep and when to use it
Characteristics of low power enabled peripherals
Tips and best practices for low power system design
How to choose the best nanoWatt device for your
application
Where to go from here!
Thank You!
Trademarks
The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KeeLoq, KeeLoq logo,
MPLAB, PIC, PICmicro, PICSTART, rfPIC, SmartShunt and UNI/O are registered
trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.
FilterLab, Hampshire, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL, SmartSensor
and The Embedded Control Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net,
dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, In ‑Circuit Serial
Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB,
MPLINK, mTouch, nanoWatt XLP, PICkit, PICDEM, PICDEM.net, PICtail, PIC32 logo,
PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total
Endurance, TSHARC, WiperLock and ZENA are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.
All other trademarks mentioned herein are property of their respective companies.
© 2009, Microchip Technology Incorporated, All Rights Reserved.
APPENDIX
Deep Sleep
Break Even Time Derivation (AN1267)
Charge used in Sleep (Power Down)
 
q   t I 
PD  PD PD 

Charge used during Deep Sleep + Required POR cycle

     
q   t I 
   t I 
  t I 

DS  PD DS 
  INIT IDD 
  POR POR 

Solving for tPD (POWERDOWN) and setting it equivalent to tBE

(BREAKEVEN):
When tBE = 0, breakeven time is reached
When tBE > 0, use Sleep
When tBE < 0, use Deep Sleep
t t
 t INITIIDD  t POR IPOR 
BE PD 

I I


 

 PD DS 

Deep Sleep
Break Even Time Derivation (AN1267)
 
q   t I 
PD  PD PD 

     
q   t I 
   t I 
  t I 

DS
PD DS 

  INIT IDD 
  POR POR 

q q
PD DS
       

 t I 
   t I 
   t I 
   t I 

 PD PD   PD PDDS 
  INIT IDD   POR POR 

       

 t I 
   t I 
   t I 
   t I 

 PD PD   PD PDDS 
  INIT IDD   POR POR 

       

 t 
   I I 
   t I 
   t I 

 PD  PD PDDS 
 INIT IDD  POR POR 
 t INITIIDD  t POR IPOR 

   
t t
BE PD 

I I


 

 PD DS 

Lithium AAA Battery
 For a Typical Lithium Application running at Room Temp (20-25ºC):

 The MCU needs to operate at and below 3V (2 x 1.5V)
{graph point 1}
 Maximizing battery life would mean being able to run down to 1.8V (2 x 0.9V)
{graph point 2}
 Safe operation with Max Battery Life = 1.8 – 3.0V operating range
Source: http://data.energizer.com/PDFs/l92.pdf
© Eveready Battery Company, Inc. Reprinted with permission.

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Low Power Design Techniques

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Low Power Design with nanoWatt XLP

Authors: Stu Chandler, Pr. TTE

V1.20 April 2010

When you finish this class you will be able to:

Defining Low Power

© 2010 Microchip Technology Incorporated. All Rights Reserved. PWR0110 Slide 3 of 98

Your customers demand low power!

Metering Consumer Medical Safety & Security

© 2010 Microchip Technology Incorporated. All Rights Reserved. PWR0110 Slide 5 of 98

Longer battery life ← Most critical requirement

© 2010 Microchip Technology Incorporated. All Rights Reserved. PWR0110 Slide 7 of 98

There are several power modes in

© 2010 Microchip Technology Incorporated. All Rights Reserved. PWR0110 Slide 8 of 98

© 2010 Microchip Technology Incorporated. All Rights Reserved. PWR0110 Slide 9 of 98

CMOS transistor switching losses VDD

© 2010 Microchip Technology Incorporated. All Rights Reserved. PWR0110 Slide 10 of 98

Capacitance (C) is affected by

© 2010 Microchip Technology Incorporated. All Rights Reserved. PWR0110 Slide 11 of 98

© 2010 Microchip Technology Incorporated. All Rights Reserved. PWR0110 Slide 12 of 98

Leakage is affected by:

© 2010 Microchip Technology Incorporated. All Rights Reserved. PWR0110 Slide 13 of 98

Average Power is the power consumed across one entire cycle

Oscilloscope with shunt resistor on V DD

VDD Capacitor Discharge Vdd

© 2010 Microchip Technology Incorporated. All Rights Reserved. PWR0110 Slide 15 of 98

Extend the idle time

Choose system elements carefully

DOZE (some devices) [active power]

IDLE (some devices) [active power]

Core OFF, peripherals ON

SLEEP [static power]

DEEP SLEEP (some devices) [static power]

Typically 35nA (3V, 25°C)

© 2010 Microchip Technology Incorporated. All Rights Reserved. PWR0110 Slide 18 of 98

Calculate the average power of the entire application

Identify the worst cases and revisit

Plot the power profile

Build, measure, and confirm the power profile

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Run A – Sample temperature sensor (800µs)

Enter power profile modes

Review & Save

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How many instruction cycles does it take to

How much energy does it take to perform an 8x8 multiply?

PIC16LF727 @1MHz @1.8V @25°C

144μW * 248μs = 35.7nJ void main (void)

PIC18LF46J11 @1MHz @2.0V @25°C B = 4;

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Note: Industry Standard Benchmark Algorithms

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Reducing system voltage impacts dynamic & static current

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Some nanoWatt XLP devices are based

on low voltage process:

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MCP1702 Linear Regulator

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Standard_Routine: // compiles to 3 instructions