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Digital Design: An Embedded Systems Approach Using Verilog: Numeric Basics
Digital Design: An Embedded Systems Approach Using Verilog: Numeric Basics
An Embedded Systems
Approach Using Verilog
Chapter 3
Numeric Basics
Portions of this work are from the book, Digital Design: An Embedded
Systems Approach Using Verilog, by Peter J. Ashenden, published by Morgan
Kaufmann Publishers, Copyright 2007 Elsevier Inc. All rights reserved.
Verilog
Numeric Basics
Representing and processing numeric
data is a common requirement
unsigned integers
signed integers
fixed-point real numbers
floating-point real numbers
complex numbers
Unsigned Integers
Non-negative numbers (including 0)
Represent real-world data
e.g., temperature, position, time, …
Also used in controlling operation of a
digital system
e.g., counting iterations, table indices
Coded using unsigned binary (base 2)
representation
analogous to decimal representation
Binary Representation
Decimal: base 10
12410 = 1×102 + 2×101 + 4×100
Binary: base 2
12410
= 1×26+1×25+1×24+1×23+1×22+0×21+0×20
= 11111002
In general, a number x is represented using n
bits as xn–1, xn–2, …, x0, where
x xn 1 2 n 1 xn 2 2 n 2 x0 20
Binary Representation
Unsigned binary is a code for numbers
n bits: represent numbers from 0 to 2n – 1
0: 0000…00; 2n – 1: 1111…11
To represent x: 0 ≤ x ≤ N – 1, need log2N
bits
Computers use
8-bit bytes: 0, …, 255
32-bit words: 0, …, ~4 billion
Digital circuits can use what ever size is
appropriate
Digital Design — Chapter 3 — Numeric Basics 5
Verilog
xn − 1 yn − 1
yn assign y = {4'b0000, x};
…
yn − 1 xn − 1
yn
ym − 2
ym − 1
Unsigned Addition
Performed in the same way as decimal
0 0 1 1 1 1 0 0 0 0 1 1 0 0 1
1 0 1 0 1 1 1 1 0 0 0 1 0 0 1
0 0 1 1 0 1 0 0 1 0 1 1 1 0 1
1 1 1 0 0 0 1 1 1 0 1 0 0 1 1 0
carry
overflow
bits
Addition Circuits
Half adder
for least-significant bits
s0 x0 y0
xi yi ci si ci+1
c1 x0 y0
0 0 0 0 0
Full adder 0
0
0
1
1
0
1
1
0
0
for remaining bits 0 1 1 0 1
si xi yi ci
1 0 0 1 0
1 0 1 0 1
ci 1 xi yi xi yi ci 1 1 0 0 1
1 1 1 1 1
Digital Design — Chapter 3 — Numeric Basics 11
Verilog
Ripple-Carry Adder
Full adder for each bit, c0 = 0
xn–1 xi yi x1 y1 x0 y0
sn sn–1 si s1 s0
Fast-Carry-Chain Adder
Also called Manchester adder
xi yi xi yi
pi gi pi ki
ci+1 0
ci+1 ci
ci
Xilinx FPGAs si si
include this
structure
Carry Lookahead
ci 1 g i pi ci
c1 g 0 p0 c0
c2 g1 p1 g 0 p0 c0 g1 p1 g 0 p1 p0 c0
c3 g 2 p2 g1 p2 p1 g 0 p2 p1 p0 c0
c4 g 3 p3 g 2 p3 p2 g1
p3 p2 p1 g 0 p3 p2 p1 p0 c0
Digital Design — Chapter 3 — Numeric Basics 15
Verilog
Carry-Lookahead Adder
Avoids chained carry circuit
x3 y3 x2 y2 x1 y1 x0 y0
g3 p3 g2 p2 g1 p1 g0 p0
c4 c0
p3 c3 p2 c2 p1 c1 p0
s3 s2 s1 s0
Adders in Verilog
Use arithmetic “+” operator
wire [7:0] a, b, s;
...
assign s = a + b;
assign {c, s} = a + b;
Unsigned Subtraction
As in decimal
b 0 1 0 1 1 0 0 0
x: 1 0 1 0 0 1 1 0
y: – 0 1 0 0 1 0 1 0
d: 0 1 0 1 1 1 0 0
borrow
bits
Subtraction Circuits
For least-significant bits
d 0 x0 y0 xi yi bi si bi+1
0 0 0 0 0
b1 x0 y0 0 0 1 1 1
0 1 0 1 1
For remaining bits 0 1 1 0 1
1 0 0 1 0
d i xi yi bi 1 0 1 0 0
1 1 0 1 0
bi 1 xi yi xi yi bi 1 1 1 1 1
Adder/Subtracter Circuits
Many systems add and subtract
Trick: use complemented borrows
Addition Subtraction
si xi yi ci
d i xi yi bi
ci 1 xi yi xi yi ci
bi 1 xi yi xi yi bi
Same hardware can perform both
For subtraction: complement y, set b0 1
Adder/Subtracter Circuits
xn–1 x 1 x0 yn–1 y1 y0
… …
xn–1 … x1 x0 yn–1 … y1 y0
cn c0
sn–1 … s1 s0
…
sn–1/dn–1 s1/d1 s0/d0
Subtraction in Verilog
module adder_subtracter ( output [11:0] s,
output ovf_unf,
input [11:0] x, y,
input mode );
assign {ovf_unf, s} = !mode ? (x + y) : (x - y);
endmodule
sn sn–1 si s1 s0
Increment/Decrement in Verilog
Just add or subtract 1
wire [15:0] x, s;
...
assign s = x + 1; // increment x
assign s = x - 1; // decrement x
Equality Comparison
XNOR gate: equality of two bits
Apply bitwise to two unsigned numbers
x0
In Verilog, x == y gives
y0 a bit result
x1
y1
1'b0 for false, 1'b1 for
eq
true
…
…
xn–1
yn–1 assign eq = x == y;
Inequality Comparison
Magnitude comparator for x > y
xn–1 xn–1 > yn–1
yn–1 gt
xn–1 = yn–1
…
x1 x1 > y1
y1 x1…0 > y1…0
x1 = y1
x0 x0 > y0
y0
Scaling by Power of 2
x xn 1 2 n 1 xn 2 2 n 2 x0 20
2 k x xn 1 2 k n 1 xn 2 2 k n 2 x0 2 k 0 2 k 1 (0)20
Scaling by Power of 2
x xn 1 2 n 1 xn 2 2 n 2 x0 2 0
x / 2 k xn 1 2 n 1 k xn 2 2 n 2 k xk 20 xk 1 2 1 x0 2 k
Scaling in Verilog
Shift-left (<<) and shift-right (>>) operations
result is same size as operand
Unsigned Multiplication
xy x yn 1 2 n 1 yn 2 2 n 2 y0 20
yn 1 x 2 n 1 yn 2 x 2 n 2 y0 x 20
Unsigned xn–1
…
xn–2 … x1 x0 yn–1 yn–2
…
… y1 y0
Multiplication
cn adder c0
sn–1 … s2 s1 s0
…
xn–1 xn–2 x1 x0 y1
…
Adders can be any of
…
xn–1 xn–2 … x1 x0 yn–1 yn–2 … y1 y0
cn adder c0
xn–1 xn–2 x1 x0 y2
Optimized multipliers … …
combine parts of
xn–1 xn–2 … x1 x0 yn–1 yn–2 … y1 y0
cn adder c0
sn–1 … s2 s1 s0
adjacent adders …
…
xn–1 xn–2 x1 x0 yn–1
… …
x … x1 x0 yn–1 yn–2 … y1 y0
cn c0
sn–1 … s2 s1
…
p2n–1 p2n–2 pn+1 pn pn–1 p2 p1 p0
Product Size
Greatest result for n-bit operands:
(2 n 1)(2 n 1) 2 2 n 2 n 2 n 1 2 2 n 2 n 1 1
Requires 22n bits to avoid overflow
Adding n-bit and m-bit operands
requires n + m bits
Gray Codes
Important for position encoders
Only one bit changes at a time
Signed Integers
Positive and negative numbers (and 0)
n-bit signed magnitude code
1 bit for sign: 0 +, 1 –
n – 1 bits for magnitude
Signed-magnitude rarely used for
integers now
circuits are too complex
Use 2s-complement binary code
2s-Complement Representation
n 1 n 2
x xn 1 2 xn 2 2 x0 2 0
Most-negative number
1000…0 = –2n–1
Most-positive number
0111…1 = +2n–1 – 1
xn–1 = 1 ⇒ negative,
xn–1 = 0 ⇒ non-negative
Since 2 n 2 20 2 n 1 1
Digital Design — Chapter 3 — Numeric Basics 38
Verilog
2s-Complement Examples
00110101
= 1×25 + 1×24 + 1×22 + 1×20 = 53
10110101
= –1×27 + 1×25 + 1×24 + 1×22 + 1×20
= –128 + 53 = –75
00000000 = 0
11111111 = –1
10000000 = –128
01111111 = +127
xn − 1 yn − 1 ...
yn assign y = {{8{x[7]}}, x};
assign y = x;
…
ym − 2 ...
y assign x = y;
Signed Negation
Complement and add 1
Note that xi 1 xi
x 1 (1 xn 1 )2 n 1 (1 xn 2 )2 n 2 (1 x0 )20 1
2 n 1 xn 1 2 n 1 2 n 2 xn 2 2 n 2 20 x0 2 0 1
( xn 1 2 n 1 xn 2 2 n 2 x0 20 )
2 n 1 (2 n 2 20 ) 1
x 2 n 1 2 n 1 x
E.g., 43 is 00101011
so –43 is 11010100 + 1 = 11010101
Digital Design — Chapter 3 — Numeric Basics 45
Verilog
Signed Negation
What about negating –2n–1?
1000…00 ⇒ 0111…11 + 1 = 1000…00
Result is –2n–1!
Recall range of n-bit numbers is not
symmetric
Either check for overflow, extend by one
bit, or ensure this case can’t arise
In Verilog: use – operator
E.g., assign y = –x;
Digital Design — Chapter 3 — Numeric Basics 46
Verilog
Signed Addition
x xn 1 2 n 1 xn 20 y yn 1 2 n 1 yn 20
n 1
x y ( xn 1 yn 1 )2 xn 20 yn 20
yields cn–1
Perform addition as for unsigned
Overflow if cn–1 differs from cn
See textbook for case analysis
Can use the same circuit for signed and
unsigned addition
Digital Design — Chapter 3 — Numeric Basics 47
Verilog
0 1 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0
72: 0 1 0 0 1 0 0 0 –63: 1 1 0 0 0 0 0 1 42: 0 0 1 0 1 0 1 0
105: 0 1 1 0 1 0 0 1 –96: 1 0 1 0 0 0 0 0 –8: 1 1 1 1 1 0 0 0
1 0 1 1 0 0 0 1 0 1 1 0 0 0 0 1 34: 0 0 1 0 0 0 1 0
Signed Subtraction
x y x ( y ) x y 1
Use a 2s-complement adder
Complement y and set c0 = 1
xn–1 x1 x0 yn–1 y1 y0
… …
xn–1 … x1 x0 yn–1 … y1 y0
cn c0
cn–1 sn–1 … s1 s0
…
sn–1/dn–1 s1/d1 s0/d0
Fixed-Point Numbers
Many applications use non-integers
especially signal-processing apps
Fixed-point numbers
allow for fractional parts
represented as integers that are implicitly
scaled by a power of 2
can be unsigned or signed
Positional Notation
In decimal
10.2410 1101 0 100 2 10 1 4 102
In binary
101.012 1 2 2 0 21 1 20 0 2 1 1 2 2 5.2510
Represent as a bit vector: 10101
binary point is implicit
Unsigned Fixed-Point
n-bit unsigned fixed-point
m bits before and f bits after binary point
x xm 1 2 m 1 x0 2 0 x1 2 1 x f 2 f
Range: 0 to 2m – 2–f
Precision: 2–f
m may be ≤ 0, giving fractions only
e.g., m= –2: 0.0001001101
Signed Fixed-Point
n-bit signed 2s-complement fixed-point
m bits before and f bits after binary point
x xm 1 2 m 1 x0 2 0 x1 2 1 x f 2 f
Range: –2m–1 to 2m–1 – 2–f
Precision: 2–f
E.g., 111101, signed fixed-point, m = 2
11.11012 = –2 + 1 + 0.5 + 0.25 + 0.0625
= –0.187510
Fixed-Point in Verilog
Use vectors with implied scaling
Index range matches powers of weights
Assume binary point between indices 0
and –1
Fixed-Point Operations
Just use integer hardware
e.g., addition: a–7
a–6 10-bit
x y (x 2 y 2 ) / 2
f f f
a–5 adder
a–4 x0
…
a3 x7
x8 s0 c–4
x9
…
Ensure binary points b–4 y0
c3
c4
are aligned
…
c5
b3 y7
b4 y8
b5 y9
Floating-Point Numbers
Similar to scientific notation for decimal
e.g., 6.02214199×1023, 1.60217653×10–19
Allow for larger range, with same
relative precision throughout the range
6.02214199×1023
exponent 2e1 1
x M 2 (1 s) 1.mantissa 2
E
Floating-Point Range
Exponents 000...0 and 111...1 reserved
Smallest value
exponent: 000...01 E = –2e–1 + 2
mantissa: 0000...00 M = 1.0
Largest value
exponent: 111...10 E = 2e–1 – 1
mantissa: 111...11 M ≈ 2.0
2e1 2 2 e1
Range: 2 x 2
Floating-Point Precision
Relative precision approximately 2–m
all mantissa bits are significant
m bits of precision
m × log102 ≈ m × 0.3 decimal digits
Example Formats
IEEE single precision, 32 bits
e = 8, m = 23
range ≈ ±1.2 × 10–38 to ±1.7 × 1038
precision ≈ 7 decimal digits
Application-specific, 22 bits
e = 5, m = 16
range ≈ ±6.1 × 10–5 to ±6.6 × 104
precision ≈ 5 decimal digits
Denormal Numbers
Exponent = 000...0 hidden bit is 0
2e1 1
x M 2 (1 s ) 0.mantissa 2
E
Floating-Point Operations
Considerably more complicated than
integer operations
E.g., addition
unpack, align binary points, adjust exponents
add mantissas, check for exceptions
round and normalize result, adjust exponent
Combinational circuits not feasible
Pipelined sequential circuits
Summary
Unsigned: x xn 1 2 n 1 xn 2 2 n 2 x0 20
Signed: x xn 1 2 n 1 xn 2 2 n 2 x0 20
Octal and Hex short-hand
Operations: resize, arithmetic, compare
Arithmetic circuits trade off
speed/area/power
Fixed- and floating-point non-integers
Gray codes for position encoding
Digital Design — Chapter 3 — Numeric Basics 68