PLECS Basics

Síxifo Falcones
ASU
Spring 2011
 Topics
• Simulation Tools
• PLECS Installation Process
– Simulink Blockset (Viewer)
– Standalone
• Graphical User Interface
• Features
– AC analysis, thermal simulation, scope, Fourier spectrum, THD,
demos, m-files (Blockset)
• Guidelines
– Drawing schematic
– Showing simulation results
• Simulation Examples
– Buck converter (open loop, closed loop, average model)
– Single-phase DC-AC converter
 Simulation Tools
• Allows for a better understanding of a
topology
• Verify controls performance
• Circuit simulator vs system simulator
• Detailed models vs ideal models
• Switching model vs average model
• Device level simulation vs system level
simulation
• Variable step vs fixed step
PLECS Model & Sub-circuits
PLECS Scope Outputs
Average Model
Single-phase DC-AC Converter
Control and PWM Stages
Simulation Results
 1-Ф DC-AC Converter
Simulink Model
[Vdc_ref] [Vconv]
Vconv(V), Vconv_cca(V), Vgrid(V)
[IL_ref] [Vconv_cca]
Vdc_ref Vdc_ref
IL_ref [Vconv]
Vdc [Vgrid]
[Vdc] IL
m m G G Vconv In Mean [Vconv_cca]
Vgrid
[IL] [IL]
Controller PLECS
PWM [Idc]
[Vgrid] Circuit
[IL_ref] IL(A), IL_ref(A)

Ii Idc In Mean [Idc_cca]

Scope
[Idc]
Power Stage
[Idc_cca]
[Ii] Idc(A) ,Idc_cca(A), Ii(A)
[IL]
[Ii]
PLECS
[Vgrid]
Probe
[Vdc]
Probe
[Vdc] [Vdc_ref] Vdc(V), Vdc_ref (V)
 Simulink Sub-systems
1 [Vdc_ref]
Vdc_ref
2 [Vdc] [Vgrid] Vgrid Sin [Sin]
Vdc
4 [Vgrid] PLL
Vgrid 1
[Sin] IL_ref

2 Gci 2
[Vdc_ref] u C/2 Gcv
E_ref e(J) IL_pk_ref m
Voltage Controller Current Controller
m_0
[Vdc] u2 C/2 3
E
IL [Vgrid]

[Vdc]

[Vdc_ref]

1
>=
m
1
NOT G

-1

>=

NOT
 Matlab M-file
% Data for Single_Phase_Inverter_Closed_Loop.mdl
clear all
clc
RL=0.01; % Inductor resistance in ohm
L=10e-3; % Inductance in H
C=1000e-6; % Capacitance in F
Ron=1e-3; % Switch ON resistance in ohm
Rsnubber=10e6; % Switch snubber resistance in ohm
fs=10e3; % Switching freq in Hz
Ts=1/fs; % Switching period in s
f0=60; % Line frequency in Hz
w0=2*pi*f0; % Line frequency in rad/s
XL=w0*L; % Inductive reactance in ohm
Vdc_ref=200; % DC link reference voltage in V
Vgrid=170; % Grid peak voltage in V
Vdc_0=Vdc_ref; % DC link initial voltage in V
Gpi=tf(Vdc_ref,[L 0]); % Plant Gain for current loop
Gpv=-tf(Vgrid,[2 0]); % Plant Gain for voltage loop
PMi=60; % Phase Margin in degrees for current loop
BWi=1000; % Bandwidth in Hz for current loop
PMv=60; % Phase Margin in degrees for voltage loop
BWv=12; % Bandwidth in Hz for voltage loop
Gci=K_Factor(Gpi,BWi,PMi); % Current Controller gain from K-Factor technique
Gcv=-K_Factor(-Gpv,BWv,PMv); % Voltage Controller gain from K-Factor technique
Goli=Gpi*Gci; % Loop gain
Golv=Gpv*Gcv;
Gcli=feedback(Goli,1); % Closed-loop gain
Gclv=feedback(Golv,1);
pole(Gcli) % Determines Closed-loop poles
pole(Gclv)
figure(1) % Opens a figure window
bode(Goli) % Generates the Bode plot of the Loop Gain
grid % Adds grid to the figure
figure(2) % Opens a figure window
bode(Golv) % Generates the Bode plot of the Loop Gain
grid % Adds grid to the figure
figure(3) % Opens a figure window
rlocus(Goli) % Generates the Root-locus plot of the Closed-loop Gain
grid % Adds grid to the figure
figure(4) % Opens a figure window
rlocus(Golv) % Generates the Root-locus plot of the Closed-loop Gain
grid % Adds grid to the figure
figure(5) % Opens a figure window
step(Gcli) % Generates the Step-response plot of the Closed-loop Gain
grid % Adds grid to the figure
figure(6) % Opens a figure window
step(Gclv) % Generates the Step-response plot of the Closed-loop Gain
grid % Adds grid to the figure
 Matlab Analysis Tools
Bode Diagram Root Locus
100 80
0.965 0.93 0.88 0.78 0.62 0.35

50 60
0.986
Magnitude (dB)

0 40

0.997
-50 20

Imaginary Axis
40 30 20 10
-100 0
-90

-20
0.997
-120
Phase (deg)

-40
0.986
-150
-60

0.965 0.93 0.88 0.78 0.62 0.35

-180 -80
1 2 3 4 5 -300 -250 -200 -150 -100 -50 0 50
10 10 10 10 10
Frequency (Hz) Real Axis
PLECS Demos (Simulink Blockset)
PLECS Demos (Standalone)
Fourier Spectrum
Total Harmonic Distortion (THD)
AC Sweep (Standalone)
AC Sweep (Simulink Blockset)
 Useful Tips
• Press Shift key to arrange PLECS subsystem ports

• Define PLECS Tags as Schematic (local) type to avoid conflict

with other subsystems

• Right-click on a block/“show name” to hide unnecessary text

• Right-click on a block/“format” to flip, rotate block
• Refer to PLECS Users Manual for more information