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    Topic V0A: Isbra Programming Example

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    Avs Revanth
    The document describes how to write a RISC-V function called IsBra that takes the binary encoding of a beq instruction and returns 1 if it represents a "branch always" instruction (bra) or 0 otherwise. It does this by extracting the rs1 and rs2 register fields from the beq encoding and checking if they are equal, indicating a bra. The function uses shifts and bitwise AND to isolate the different fields, compares the registers, and returns the appropriate value.

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    Topic V0A: Isbra Programming Example

    Uploaded by

    Avs Revanth
    5 views10 pages
    The document describes how to write a RISC-V function called IsBra that takes the binary encoding of a beq instruction and returns 1 if it represents a "branch always" instruction (bra) or 0 otherwise. It does this by extracting the rs1 and rs2 register fields from the beq encoding and checking if they are equal, indicating a bra. The function uses shifts and bitwise AND to isolate the different fields, compares the registers, and returns the appropriate value.

    Original Description:

    IsBra Programming Example

    Original Title

    V0A-IsBraExample

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    The document describes how to write a RISC-V function called IsBra that takes the binary encoding of a beq instruction and returns 1 if it represents a "branch always" instruction (bra) or 0 otherwise. It does this by extracting the rs1 and rs2 register fields from the beq encoding and checking if they are equal, indicating a bra. The function uses shifts and bitwise AND to isolate the different fields, compares the registers, and returns the appropriate value.

    Copyright:

    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd
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    Download as pptx, pdf, or txt
    5 views10 pages

    Topic V0A: Isbra Programming Example

    Uploaded by

    Avs Revanth
    The document describes how to write a RISC-V function called IsBra that takes the binary encoding of a beq instruction and returns 1 if it represents a "branch always" instruction (bra) or 0 otherwise. It does this by extracting the rs1 and rs2 register fields from the beq encoding and checking if they are equal, indicating a bra. The function uses shifts and bitwise AND to isolate the different fields, compares the registers, and returns the appropriate value.

    Copyright:

    © All Rights Reserved
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    Topic V0A

    IsBra Programming Example


    Sample Question
    One way to implement a “branch always” (bra) instruction, is to use the
    beq instruction and to make both registers the same. For example:
    beq t0, t0, LABEL

    Binary format of a branch instruction:


    31 25 24 20 19 15 14 12 11 7 6 0

    imm[12|10:5] rs2 rs1 func3 imm[4:1|11] op

    Write the RISC-V code for a function IsBra that receives the binary code of
    a beq instruction in a0 and returns 1 in a0 if it is a bra and returns 0 in
    a0 otherwise.
    Sample Question
    Write the RISC-V code for a function IsBra:

    • Input parameter:
    • a0: binary code of a beq instruction;
    • Return value:
    • a0 = 1: the beq instruction is a bra
    • a0 = 0: the beq instruction is not a bra
    31 25 24 20 19 15 14 12 11 7 6 0

    a0 = imm[12|10:5] rs2 rs1 func3 imm[4:1|11] op

    First we shift the content of a0 to the right by 15 bits:


    srli t0, a0, 15
    31 17 16 10 9 5 4 0
    t0 = 0000 0000 0000 000 imm[12|10:5] rs2 rs1

    Now we AND the result with 0x01F:


    andi t1, t0, 0x01F
    31 17 16 10 9 5 4 0
    t0 = 0000 0000 0000 000 imm[12|10:5] rs2 rs1
    31 5 4 0
    0x01F = 0000 0000 0000 000 0 0000 00 00 000 1 1111
    31 5 4 0
    t1 = 0000 0000 0000 000 0 0000 00 00 000 rs1
    31 25 24 20 19 15 14 12 11 7 6 0

    a0 = imm[12|10:5] rs2 rs1 func3 imm[4:1|11] op

    Then we shift the content of a0 to the right by 20 bits:


    srli t0, a0, 20
    31 17 16 12 11 5 4 0
    t2 = 0000 0000 0000 000 0 0000 imm[12|10:5] rs2

    Now we AND the result with 0x01F:


    andi t3, t2, 0x01F
    31 17 16 12 11 5 4 0
    t2 = 0000 0000 0000 000 0 0000 imm[12|10:5] rs2
    31 5 4 0
    0x01F = 0000 0000 0000 000 0 0000 0000 000 1 1111
    31 5 4 0
    t3 = 0000 0000 0000 000 0 0000 0000 000 rs2
    Finally, we use a beq instruction to find if rs1 and rs2 are the same
    register:
    beq t1, t3, braTrue
    31 5 4 0
    t1 = 0000 0000 0000 000 0 0000 00 00 000 rs1
    31 5 4 0
    t3 = 0000 0000 0000 000 0 0000 0000 000 rs2
    IsBra:
    srli t0, a0, 15 # t0 ← a0 >> 15
    andi t1, t0, 0x01F # t1 ← rs1
    srli t2, a0, 20 # t2 ← a0 >> 20
    andi t3, t2, 0x01F # t2 ← rs2
    beq t1, t3, braTrue # if rs1 = rs2 goto braTrue
    addi a0, zero, 0 # a0 ← 0
    jalr zero, ra, 0 # return Textbook uses the syntax:
    braTrue:
    addi a0, zero, 1 # a0 ← 1 jalr zero, 0(ra)
    jalr zero, ra, 0 #return
    31 25 24 20 19 15 14 12 11 7 6 0

    a0 = imm[12|10:5] rs2 rs1 func3 imm[4:1|11] op


    31 25 24 20 19 15 14 12 11 7 6 0

    t1 = 0000 000 0 0000 1111 1 000 0000 0 000 0000


    31 25 24 20 19 15 14 12 11 7 6 0

    t2 = 0000 000 0 0000 rs1 000 0000 0 000 0000

    Alternatively, we can AND a0 with 0x000F8000 but you cannot use a


    constant larger than 12 bits in an andi instruction:
    li t0, 0x0F8 # t0 ← 0x0000 00F8
    slli t1, t0, 12 # t1 ← 0x000F 8000
    OR
    lui t1, 0x000F8 # t0 ← 0x000F 8000

    Now we can AND a0 with a1 to obtain:


    and t2, t1, a0
    31 25 24 20 19 15 14 12 11 7 6 0

    a0 = imm[12|10:5] rs2 rs1 func3 imm[4:1|11] op


    31 25 24 20 19 15 14 12 11 7 6 0

    t4 = 0000 000 1 1111 0000 0 000 0000 0 000 0000


    31 25 24 20 19 15 14 12 11 7 6 0

    t5 = 0000 000 rs2 0000 0 000 0000 0 000 0000

    Now we can do something similar to extract the rs2 field:


    li t3, 0x01F # t0 ← 0x0000 001F
    slli t4, t0, 20 # t1 ← 0x01F0 0000
    OR
    lui t4, 0x01F00 # t0 ← 0x01F0 0000

    Now we can AND a0 with a1 to obtain:


    and t5, t4, a0
    31 25 24 20 19 15 14 12 11 7 6 0

    a0 = imm[12|10:5] rs2 rs1 func3 imm[4:1|11] op


    31 25 24 20 19 15 14 12 11 7 6 0

    t1 = 0000 000 0 0000 1111 1 000 0000 0 000 0000


    31 25 24 20 19 15 14 12 11 7 6 0

    t2 = 0000 000 0 0000 rs1 000 0000 0 000 0000


    31 25 24 20 19 15 14 12 11 7 6 0

    t4 = 0000 000 1 1111 0000 0 000 0000 0 000 0000


    31 25 24 20 19 15 14 12 11 7 6 0

    t5 = 0000 000 rs2 0000 0 000 0000 0 000 0000


    31 25 24 20 19 15 14 12 11 7 6 0

    t6 = 0000 000 0 0000 rs2 000 0000 0 000 0000


    Finally we can shift t5 to the right by 5 before comparing with t2:
    srli t6, t5, 5 # t6 ← t5 >> 5
    beq t6, t2, braTrue
    …
    00…0 11…1 00…0 00…0 00…0 11…1
    00…0 00…0 00…0 00…0

    Recap

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