ECE 3013-Linear Integrated Circuits: Module-Vi

ECE 3013-Linear Integrated Circuits
MODULE-VI
PLL & TIMERS
Dr.S.Umadevi
Associate Professor, SENSE,
VIT Chennai
Module-VI
PLL AND TIMERS
Phase detector comparator
Voltage Controlled Oscillator (VCO)
Phase Locked Loop (PLL)
PLL applications
operating modes 555 timer
Astable and Monostable operation and applications
PHASE DETECTOR
1
1
PHASE DETECTOR
 Two types of phase detectors used, analog and digital.
 Analog phase detector

 Switch type
 Balanced modulator
 Digital phase detector

 Using XOR gate
 Using RS flip flop
MODULE- VI 2
2
PHASE DETECTOR
Analog Phase detector (Switch Type)
 An electronic switch S is opened and closed by signal coming from VCO

(normally a square wave). The input signal Vs, therefore, chopped at a
repetition rate determined by VCO frequency.
MODULE- VI 3
3
PHASE DETECTOR
MODULE- VI 4
4
PHASE DETECTOR
 A phase comparator is basically a multiplier which multiplies the input signal (vs = Vs sin 2π fst) by the
VCO signal (vo = Vo sin (2π fot + φ). Thus the phase comparator output is,
Ve = KVsVo sin (2 π fSt) sin (2π f0t + φ)
where K is the phase comparator gain
φ is the phase shift b/n the input signal and VCO output.
 The output of the phase comparator when filtered through a low pass filter gives an error signal which
is the average value of the output waveform shown by dotted line.
 It may be seen that the error voltage is zero when the phase shift between the two inputs is 90°. So,
for perfect lock, the VCO output should be 90° out of phase with respect to the input signal.
MODULE- VI 5
5
PHASE DETECTOR
 After simplification,
Ve = (KVSVo /2) [cos(2π fst - 2π fot – φ) - cos(2π fst +2π fot + φ)]
when at lock, fs = fo
Ve = (KVSVo /2) [cos(– φ) - cos(2π x 2fot + φ)]
 The double frequency term is eliminated by the low pass filter and the dc signal is applied to the
modulating input terminal of a VCO.
 It can be seen that in the perfect locked state (fs = fo), the phase shift should be 90° (cos 90°=0), in
order to get zero error signal, that is, ve = 0.
MODULE- VI 6
6
PHASE DETECTOR
DIGITAL PHASE DETECTOR – Using XOR gate
 The output of the XOR gate is high when only one of the inputs signals fs or fo is high. This type of
detector is used when both the input signals are square waves.
 The input and output waveforms for fs = fo are shown in Fig. (b). In this figure, fs is leading fo by φ
degrees.
 It can be seen that the maximum dc output voltage occurs when the phase difference is π because
the output of the gate remains high throughout.
MODULE- VI 7
7
PHASE DETECTOR
MODULE- VI 8
8
VOLTAGE
CONTROLLED
OSCILLATOR (VCO)
9
9
VOLTAGE CONTROLLED OSCILLATOR
MODULE- VI 10
10
MODULE- VI 11
11
MODULE- VI 12
12
MODULE- VI 13
13
MODULE- VI 14
14
PHASE LOCKED
LOOP (PLL)
15
15
PHASE LOCKED LOOP
 The phase-locked loop (PLL) is an important building block of linear systems
 phase-locked loop, an electronic circuit that controls an oscillator so that it

maintains a constant phase angle (i.e., lock) on the frequency of an input, or
reference signal.
 A PLL ensures that a communication signal is locked on a specific frequency

and can also be used to generate, modulate and demodulate a signal and
divide a frequency.
 Now with the advanced IC technology, PLLs are available as inexpensive

monolithic ICs.
MODULE- VI 16
16
PHASE LOCKED LOOP
 PLL technique for electronic frequency control is used today in satellite
communication systems, air borne navigational systems, FM communication
systems, computers etc.
MODULE- VI 17
17
PHASE LOCKED LOOP
The basic block schematic of the consists of:
Phase detector/comparator
A low pass filter
An error amplifier
A Voltage Controlled Oscillator (VCO)
 Phase detector/comparator: compares the phase of two signals & generates a

voltage according to the phase difference b/n the two signals.
 Low pass filter: This filter is used to filter the high frequency output from the
phase comparator in the PLL.
MODULE- VI 18
18
PHASE LOCKED LOOP
Error amplifier: to provide a amplifier error voltage signal to VCO.
 Voltage controlled oscillator (VCO): it generates the output radio frequency

signal.
 If an input signal Vs of frequency fs is applied to the PLL, the phase detector

compares the phase and frequency of the incoming signal to that of the output
V0 of the VCO.
 If the two signals differ in frequency and/or phase, an error voltage ve is

generated.
MODULE- VI 19
19
PHASE LOCKED LOOP
 The phase detector is basically a multiplier and produces the sum (fs + fo)
and difference (fs - fo) components at its output.
 The high frequency component (fs + f0) is removed by the low pass filter and
the difference frequency component is amplified and then applied as control
voltage Vc to VCO.
 The signal Vc shifts the VCO frequency in a direction to reduce the frequency
difference between fs and f0.
 Once this action starts, we say that the signal is in the capture range.
MODULE- VI 20
20
PHASE LOCKED LOOP
 The VCO continues to change frequency till its output frequency is exactly
the same as the input signal frequency. The circuit is then said to be locked.
 Once locked, the output frequency fo of VCO is identical to fs except for a

finite phase difference φ
 Thus, a PLL goes through three stages

(i) free running
(ii) capture and
(iii) locked or tracking.
MODULE- VI 21
21
PHASE LOCKED LOOP
MODULE- VI 22
22
PHASE LOCKED LOOP
 Lock-in Range: The range of frequencies over which the PLL can maintain lock
with the incoming signal is called the lock-in range or tracking range.
 Capture Range: The range of frequencies over which the PLL can acquire lock
with an input signal is called the capture range.
 Pull-in time: The total time taken by the PLL to establish lock is called pull-in
time.
MODULE- VI 23
23
PLL APPLICATIONS
24
24
PLL APPLICATIONS
MODULE- VI 25
25
PLL APPLICATIONS
MODULE- VI 26
26
PLL APPLICATIONS
MODULE- VI 27
27
PLL APPLICATIONS
MODULE- VI 28
28
PLL APPLICATIONS
MODULE- VI 29
29
PLL APPLICATIONS
MODULE- VI 30
30
IC555 - TIMER
37
37
IC555 - TIMER
 The 555 timer IC was introduced in the year 1970 by Signetic
Corporation and gave the name SE/NE 555 timer.
 It is basically a monolithic timing circuit that produces accurate and

highly stable time delays or oscillation.
 Apart from its applications as a monostable multivibrator and astable

multivibrator, a 555 timer can also be used in dc-dc converters,
waveform generators, temperature measurement and control devices,
voltage regulators etc.
MODULE- VI 38
38
IC555 - TIMER
Features
 To generate a time delay of few milliseconds to few hours
 It operates from a wide range of power supplies : + 5 V to + 18 V
 Two operating modes: Monostable & Astable
 Available IC packages: 8-pin Metal CAN, 8-Pin DIP, 14-Pin DIP
 It has a temperature stability, equivalently 0.005 %/ °C.
 Operating temperature range: -550c to 1250c
 Sinking or sourcing 200 mA of load current.
MODULE- VI 39
39
IC555 - TIMER
MODULE- VI 40
40
IC555 - TIMER
MODULE- VI 41
41
IC555 - TIMER
IC555 - BLOCK DIAGRAM
MODULE- VI 42
42
IC555 - TIMER
Pin Description
 Pin 1: Grounded Terminal: All the voltages are measured with respect to the
Ground terminal.
 Pin 2: Trigger Terminal: The trigger pin is used to feed the trigger input then
the 555 IC is set up as a monostable multivibrator.
 Pin 3: Output Terminal: Output of the timer is available at this pin.
 Pin 4: Reset Terminal: Whenever the timer IC is to be reset or disabled, a

negative pulse is applied to pin 4.
MODULE- VI 43
43
IC555 - TIMER
Pin Description
 Pin 5: Control Voltage Terminal: The threshold and trigger levels are
controlled using this pin.
 Pin 6: Threshold Terminal: This is the non-inverting input terminal of

comparator 1, which compares the voltage applied to the terminal with a
reference voltage of 2/3 VCC.
 Pin 7 : Discharge Terminal: This pin is connected to the collector of transistor

and mostly a capacitor is connected between this terminal and ground.
 Pin 8: Supply Terminal: A supply voltage of + 5 V to + 18 V is applied

MODULE- VI 44
44
INTERNAL BLOCKS OF IC555 TIMER
IC555 TIMER-ASTABLE MULTIVIBRATOR
https://
www.wisc-online.com/learn/em-solid-state/em-timers-rr0008/
sse8106/the-555-astable-multivibrator
IC555 TIMER-MONOSTABLE MULTIVIBRATOR
https://www.wisc-online.com/learn/em-solid-state/em-timers-r
r0008/sse8306/the-555-monostable-multivibrator
IC555 - TIMER
Operating Modes
 The most common types of outputs can be categorized by the following:
 Monostable mode: in this mode, the 555 functions as a "one-shot". Applications include
timers, missing pulse detection, bounce free switches, touch switches, frequency divider,
capacitance measurement, pulse-width modulation (PWM) etc.
MODULE- VI 45
45
IC555 - TIMER
Operating Modes
 The most common types of outputs can be categorized by the following:
 Astable - free running mode: the 555 can operate as an oscillator. Uses include LED and
lamp flashers, pulse generation, logic clocks, tone generation, security alarms, pulse
position modulation, etc.
MODULE- VI 46
46
MONOSTABLE
MULTIVIBRATOR
47
47
MONOSTABLE MULTIVIBRATOR
Monostable Multivibrator
MODULE- VI 48
48
MODULE- VI 49
49
 In monostable mode the 555 timer outputs a high pulse, which begins when
the trigger pin is set low (less than 1/3Vcc, as explained in the previous step,
this is enough to switch the output of the comparator connected to the trigger
pin).
 The duration of this pulse is dependent on the values of the resistor R and
capacitor C. When the trigger pin is high, it causes the discharge pin (pin 7) to
drain all charge off the capacitor.
 This makes the voltage across the capacitor (voltage of pin 6) = 0.
MODULE- VI 50
50
 When the trigger pin gets flipped low, the discharge pin is no longer able to
drain current, this causes charge to build up on the capacitor according to the
equation below.
 Once the voltage across the capacitor (the voltage of pin 6) equals 2/3 of the
supply voltage (again, as explained in the previous step, this is enough to
switch the output of the comparator connected to pin 6), the output of the
555 is driven back low.
MODULE- VI 51
51
MODULE- VI 52
52
MODULE- VI 53
53
Monostable Multivibrator - Applications
MODULE- VI 54
54
Module – VI 55
55
MODULE- VI 56
56
MODULE- VI 57
57
MODULE- VI 58
58
MODULE- VI 59
59
MODULE- VI 60
60
MODULE- VI 61
61
ASTABLE
MULTIVIBRATOR
62
62
ASTABLE MULTIVIBRATOR
Astable Multivibrator
MODULE- VI 63
63
MODULE- VI 64
64
MODULE- VI 65
65
MODULE- VI 66
66
MODULE- VI 67
67
MODULE- VI 68
68
MODULE- VI 69
69
MODULE- VI 70
70
MODULE- VI 71
71
MODULE- VI 72
72
MODULE- VI 73
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MODULE- VI 74
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MODULE- VI 75
75
THANK YOU
by i.S
de v
a
Um

ECE 3013-Linear Integrated Circuits: Module-Vi

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ECE 3013-Linear Integrated Circuits

 Two types of phase detectors used, analog and digital.

 Analog phase detector

 Digital phase detector

 An electronic switch S is opened and closed by signal coming from VCO

 phase-locked loop, an electronic circuit that controls an oscillator so that it

 A PLL ensures that a communication signal is locked on a specific frequency

 Now with the advanced IC technology, PLLs are available as inexpensive

 Phase detector/comparator: compares the phase of two signals & generates a

 Voltage controlled oscillator (VCO): it generates the output radio frequency

 If an input signal Vs of frequency fs is applied to the PLL, the phase detector

 If the two signals differ in frequency and/or phase, an error voltage ve is

 Once locked, the output frequency fo of VCO is identical to fs except for a

 Thus, a PLL goes through three stages

 It is basically a monolithic timing circuit that produces accurate and

 Apart from its applications as a monostable multivibrator and astable

IC555 - BLOCK DIAGRAM

 Pin 3: Output Terminal: Output of the timer is available at this pin.

 Pin 4: Reset Terminal: Whenever the timer IC is to be reset or disabled, a

 Pin 6: Threshold Terminal: This is the non-inverting input terminal of

 Pin 7 : Discharge Terminal: This pin is connected to the collector of transistor

 Pin 8: Supply Terminal: A supply voltage of + 5 V to + 18 V is applied

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