Unit – III

SUBSYSTEM DESIGN - I
⮚Adders
⮚Transmission based Adder
⮚Carry look-ahead adder
⮚Manchester carry chain adder
⮚Carry Skip Adder
⮚Carry Select Adder
⮚Barrel Shifter
⮚Multipliers
⮚ Array Multiplier
⮚ Booth Multiplier
⮚ALUs
 Adders

• Full Adder Truth Table

• Combinational Adder – simplest approach, gate level adder to yield the

required majority logic functions.
• From Truth Table
 Contd.,

• For n-cascaded stages, the delay associated with adder is

Ta = n∙Tc
• Where Ta – The total add time
• n – The total number of adder stages
• Tc – The delay of one carry stage
 Contd.,

• To optimize the carry delay, the inverter at the output of the

carry gate can be omitted, then every stage operates with a
complementary data which decreases the delay.
N-bit Ripple Carry Adder
 N-Bit Serial Adder

• At time t, the SUM is calculated and the carry is stored in the

flip flop. At time t+1, the SUM uses CARRY(t) to calculate
new SUM as
 Contd.,

• The combinational adder can be optimized in three ways i.e.,

1. Arrange the transistors switched by the carry in signal (C) close to

the output, which enables the input signals to settle the gate such
that the C transistors are least influenced by body effect
 Contd.,

• 2. Make all transistors in the sum gate whose gate signals are connected to
CARRY_BAR minimum size, which minimizes the capacitive load on this
signal. Keep routing on this signal to a minimum and minimize the use of
diffusion as a routing layer.

• 3. Sizing of series transistors can be determined by simulation. It may or

may not pay to increase the size of the series n-transistors and p-transistors.

– It may pay to increase the size of the transistors connected to A and B

in the carry gate in a ripple carry adder, as these signals will have time
to settle in the upper bits of the adder while the carry is rippling.

– It may pay to increase the size of the C transistors in the carry gate to
override the effects of stray capacitance. For a parallel adder, the SUM
gate transistors may be made minimum size, while for a serial adder
the CARRY and SUM delays would have to be more balanced.
 Dynamic Serial
Adder Schematic

Device
 Transmission Gate Adder

• XOR Gate
– When signal A is high, A_Bar is low. Transistor pair 1 and 2 thus act as
an inverter, with B_Bar appearing at the output. The transmission gate
formed by transistor pair 3 and 4 is open.
– When signal A is low, A_Bar is high. The transmission gate (3+40 is
now closed, passing B to the output. The inverter pair (1+2) are
disabled.
• To construct an xnor gate, reverse the connections of A and A_Bar
 Contd.,

• Transmission
Gate Adder
 Contd.,

• Complete
TG Adder
 Carry Look Ahead Adder

• The linear growth of adder carry delay with

the size of the input word may be improved by
calculating the carries to each stage in parallel.

• The carry of the ith stage Ci, may be expressed

as
 Contd. ,

• The size of the gates needed to implement this logic is large,

hence practically limited to four Stages.
 Contd.,

• Gate
level
impleme
ntation
of Carry
Look
Ahead
Logic
 Contd. ,

• Domino
Carry
Look
ahead
Adder
 Contd. ,

• Static
Carry
Look
ahead
gate
Manchester Carry Adder
• The efficiency of the domino
carry chain can be enhanced by
precharging at appropriate points.

• When CLOCK is low, the output

node is precharged by the p pull-
up transistor.

• When CLOCK goes high, the n

pull-down transistor turns on. If
the carry generate (A.B) is true,
then the output node discharges.

• If carry propagate (A+B) is true,

then a previous carry may be
coupled to the output node,
conditionally discharging it.
Carry Skip/ Bypass Adder
 Contd.,

• No longer need the intermediate carry gates, as the carry values are available in a distributed fashion.

• For a 4-bit adder to reduce the number of series propagate transistors, which reduce the body effect.

• If all propagate signals are true and C is high, six series n-transistors pull the output node low so that worst
case propagation time can be reduced.

• Dynamic AND gate turns on a carry bypass signal if all carry propagates are true. As the node capacitance
of carry look ahead gate reduces to half of Manchester chain.

• It improves the overall speed of the adder.

Carry Select
Adder
 Carry Select Adder

• K is the MUX delay

16 – Bit Regular Carry Select Adder
16 – Bit Modified Carry Select Adder
 Design of 4-Bit Shifter

• The bit shifts are sometimes considered bitwise operations, because they treat a

value as a series of bits rather than as a numerical quantity. In these operations the
digits are moved, or shifted, to the left or right.

• Registers in a computer processor have a fixed width, so some bits will be "shifted
out" of the register at one end, while the same number of bits are "shifted in" from
the other end; the differences between bit shift operators lie in how they determine
the values of the shifted-in bits.

• Types of shifts
– Arithmetic Shift
– Logical Shift
– Rotate Shift
 Arithmetic Shift

Left arithmetic shift Right arithmetic shift

Logical Shift

Left logical shift Right logical shift

 Circular Shift/ Rotate

Left circular shift or rotate Right Circular shift or rotate

Rotate through Carry

Left rotate through carry Right rotate through carry

 Design of 4-Bit Shifter

• The shifter must have

• Switch and Relay based switching networks – the crossbar switch

• If all switches are closed, then all inputs are connected to all outputs in one
glorious short circuit.

• 16 control signals (SW00 – SW15) one for each transistor switch, must be
provided to drive the crossbar switch, this complexity is highly undesirable.
Switch and Relay based switching networks – the
crossbar switch
 4 x 4 Barrel Shifter

• The interbus switches have their gate inputs connected in a staircase fashion in groups
four and with four shift control inputs which must be mutually exclusive in the active
state.

• We can use CMOS transmission gate

• High regularity and generality.

 Multipliers

• Applications – Correlation, Convolution, Filtering, frequency

analysis.

• Traditional technique – successive additions and shifts in

which each addition is conditional on one of the multiplier
bits.
 Contd.,

• Multiplication process can be done in

– Evaluation of Partial Product
– Accumulation of the shifted partial product.

• Binary multiplication is equivalent to a logical AND

operation.

• Choice of multiplier depends on speed, throughput, numerical

accuracy and area.
Array Multiplier
Array Multiplier
Braun Array Multiplier using carry save multiplication
Booth Multiplier
Modified Booth Multiplier
ALUs
4 - Bit ALU